Analog Circuit Design: High-Speed Analog-to-Digital Converters; Mixed Signal Design; PLL’s and Synthesizers

410 Pages·2000·16.68 MB·English

by  M. Steyaert

ANALOG CIRCUIT DESIGN
Analog Circuit Design
High-Speed Analog-to-Digital Converters;
Mixed-Signal Design; PLL's and Synthesizers
Edited by
Rudy J. van de Plassche
Broadcom Netherlands B. V., Bunnik
Johan H. Huijsing
Delft University of Technology
and
Willy Sansen
Katholieke Universiteit Leuven
••
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5002-4 ISBN 978-1-4757-3198-9 (eBook)
DOI 10.1007/978-1-4757-3198-9
Printed on acid-free paper
All Rights Reserved
© 2000 Springer Science+B usiness Media New York
Originally published by Kluwer Academic Publishers in 2000
Softcover reprint of the hardcover 1st edition 2000
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording or by any information storage and
retrieval system, without written permission from the copyright owner.
Table of Contents
Part 1: High-Speed Analog-to-Digital Converters
Introduction 1
Speed-Power-Accuracy Trade-off in high-speed Analog-to-digital
converters: Now in the future ...
M. Steyaert and K. Uyttenhove 3
A dual mode 700 Msamples/s 6-bit, 200 Msamples/s 7-bit AID converter in
0.25 micron digital CMOS
K. Nagaraj, D. Martin, M. Wolfe, R. Chattopaday, S. Pavan, J. Cancio and T.R.
Viswanathan 25
A 3.3 V 12b 50-Ms/s AID converter in 0.6 micron CMOS with over SO
dB SFDR
H. Pan, M. Segami, M. Choi, J. Cao, F. Hatori and A.A. Abidi 47
A 10-bit 20-30 MSPS CMOS subranging ADC with 9.5 Effective bits at
Nyquist
B. Brandt and J. Lutsky 75
A 2.5 MHz output-rate delta-sigma ADC with 90dB SNR and 102dB
SFDR
I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao and S.
Chan 95
A 13-bit bandpass sigma-delta modulator for 10.7 MHz digital IF with a 40
MHz sampling rate
J. van Engelen 119
Part II: Mixed Signal Design
Introduction 139
System-level design issues for mixed-signal ICs and telecom frontends
G. Gielen 141
Mixed signal: Design issues
H. Casier 167
v
vi
Top-down design of mixed-signal circuits
K. Kundert _____ __ _ _ _ _ ____ _ __ ___________ _ _ _ __
Computer aided design for integrated systems
P.M. Stubbe _________________________ ·····-----------
Mixed mode sigma-delta ADC design for high-quality audio
G. Cesura, A. Venca, V. Colonna, G. Gandolfi, S. Dalle Peste and R.
Castello
······-··-··············-··-···············--·······-··-·········-···············--···-·······-·········-··-·--··-···-···-········--·····-·-·······-·······--······-·······--·······--·········-······--······-·-······-·······-·-·······--·········-·-·······-·····-·····-·-·······-·······················--··-·····-·····--······--·····-·"·""7
Mixed mode telecom design
D.M.W. Leenaerts and P.W.H. de Vreede 247
Part Ill: PLL's and Synthesizers
Introduction -····-·····--····--··--······-··· ·--······-·-···-·-·-·····--······--·····--·····-·-··-·-····--·····-·····- ····--···--·····--··-·-·-·--·····- 267
On placing multiple inductor-based VCOs on the same mixed-signal
substrate
J. Parker and M. Altmann 269
Fully integrated CMOS frequency synthesizers for wireless
communications
B. De Muer and M. Steyaert 287
Design and optimization of RFCMOS-circuits for integrated PLL's and
synthesizers
M. Tiebout .. _· ···············-····---- _· ·-······--- __ _____ -··········-·····-·····--········------- ___ 325
Frequency synthesis for integrated transceivers
J-W. Eikenbroek and S. Mattison 339
PLL frequency synthesizers: Phase noise issues and wide-band loops
M. de Queiroz Tavares__________ _______ __________ _ __________________ 357
Low-power circuits for RF- frequency synthesizers in the low GHz range
D. Pfaff and Q. Huang________________ ___ ______ ___ ________________ 383
Preface
This book contains the extended and revised editions of all the talks of the
ninth AACD Workshop held in Hotel Bachmair, April 11 - 13 2000 in
Rottach-Egem, Germany. The local organization was managed by Rudolf
Koch of Infineon Technologies AG, Munich, Germany.
The program consisted of six tutorials per day during three days. Experts in
the field presented these tutorials and state of the art information is
communicated.
The audience at the end of the workshop selects program topics for the
following workshop.
The program committee, consisting of Johan Huijsing of Delft University of
Technology, Willy Sansen of Katholieke Universiteit Leuven and Rudy van
de Plassche of Broadcom Netherlands BV Bunnik elaborates the selected
topics into a three-day program and selects experts in the field for
presentation.
Each AACD Workshop has given rise to publication of a book by Kluwer
entitled "Analog Circuit Design". A series of nine books in a row provides
valuable information and good overviews of all analog circuit techniques
concerning design, CAD, simulation and device modeling. These books can
be seen as a reference to those people involved in analog and mixed signal
design.
The aim of the workshop is to brainstorm on new and valuable design ideas
in the area of analog circuit design. It is the hope of the program committee
that this ninth book continues the tradition of emerging contributions to the
design of analog and mixed signal systems in Europe and the rest of the
world.
Rudy J. van de Plassche
Broadcom Netherlands BV.
vii
High-Speed Analog-to-Digital Converters
R.J. van de Plassche
The application of digital techniques to process analog signals in systems on
a chip continues to be a very a crucial part of such a system. Analog-to
digital converters with analog preprocessing circuitry are combined with
digital circuitry on the same chip using standard digital CMOS process
technology. The scaling of CMOS technology to reduce power and increase
the system size results in a reduction of the available supply voltage. Soon
this supply voltage will reach 1 V or below. To design an analog-to-digital
converter using such a small supply voltage will be a tremendous challenge.
Furthermore the susceptibility of the analog circuit part to ground bounces
and (digital) substrate noise injection has to be taken into account. In this
session the progress in high-speed analog-to-digital converter design will be
reported.
In the first paper by Steyaert et al. The influence of technology scaling on
the performance of converters is discussed. This paper gives insight in future
problems and possibilities to design high-performance converters.
In the second paper by Nagaraj et al, examples of a 6-bit and a 7-bit high
speed analog-to-digital converter are shown. These converters use a standard
0.25 micron digital CMOS technology.
The third paper describes a 12-bit CMOS analog-to-digital converter using
folding an interpolation. This converter has been optimized to obtain a large
Spurious Free Dynamic Range of 80 dB suitable for radio receiver
applications.
The fourth paper by Brandt et al, shows what can be obtained using a
subranging architecture to optimize performance, power and dies size. A 1O
bit converter with 9.5 effective bits is reported.
In the field of sigma-delta conversion Fujimori et al, shows what techniques
can be used to optimize the performance of sigma-delta modulator with a
large signal bandwidth and a limited oversampling factor. Over a bandwidth
of2.5 MHz 90 dB signal-to-noise ratio is obtained with and SFDR of 102
dB.
R. J. van de Plassche eta/. (eds.),Analog Circuit Design, 1-2.
© 2000 Kluwer Academic Publishers.
2
The last contribution by van Engelen discusses stability and design criteria
for a bandpass sigma-delta modulator to be used in AM/FM radio systems.
This continuous time bandpass modulator obtains at 10.7 MHz Intermediate
Frequency input signal a resolution of 13-bit with a sampling frequency
between 40 and 80 MHz.
Speed-Power-Accuracy Trade-off
In high-speed Analog-to-digital converters:
Now and in the future ...
M. Steyaert and K. Uyttenhove
K.U.Leuven, ESAT-MICAS
Kardinaal Mercierlaan 94, 3001 Heverlee, Belgium
Abstract
High-speed analog-to-digital converters (ADC's) are an essential part
in a signal processing system. Radar applications and hard disk drive
read channels require very high conversion speeds and relatively low
resolutions (6-8 bits) [1][4]. Since several ADC's may be needed in a
"system-on-chip", the ADC should only consume a small fraction of
the total power budget [15]. In this article, a fundamental trade-off
between speed, power and accuracy for high-speed converters is
shown. This trade-off only depends on the matching data of the used
process. Technology-scaling issues influencing this trade-off will be
discussed. An important factor is the supply voltage; the never-ending
story of technology trends towards smaller transistor dimensions has
resulted to date in deep sub-micron transistors. The consequence is the
downscaling of the power supply voltages, to date even lower than
2V, with almost the same threshold voltages of the CMOS transistors
(in order to keep the leakage current in digital circuits small enough).
This voltage scaling will have an impact on the previous mentioned
trade-off between speed, power and accuracy. In the first section,
high-speed ADC' s architectures are presented.
In the second section the impact of mismatch or accuracy in analog
circuits (especially in high-speed ADC's) and the impact on power
drain is discussed. Secondly in section three some fundamental
limitations of analog integrated circuit design in the trade-off between
speed, accuracy and power drain are analysed. In the following section
the impact of the supply-voltage scaling on this trade-off is studied.
After this, some modifications are presented to circumvent this trade
off, and the article is ended with a conclusion.
3
R. J. van de Plassche et al. (eds.), Analog Circuit Design, 3-24.
© 2000 Kluwer Academic Publishers.
4
High-speed ADC architecture
An ND conversion algorithm is a description of the functional
operation of the ADC. The architecture of the ADC is the translation
of this algorithm in hardware. The choice of architecture is strongly
related to the system design. This system design is ruled by the trade
off between performance and hardware cost of its building blocks.
From literature, high-speed, low/medium resolution ADC
architectures can be roughly divided in three groups: full flash,
folding/interpolating and pipelined architectures. Each of these
architectures has its own place in the resolution-bandwidth picture
shown in Figure 1 .
Flash-type architectures are typically the fastest structures that can be
used to implement low resolution ADC' s. Figure 2 presents a typical
block diagram of a N-bit flash converter. The resistive ladder
subdivides the converter external reference voltages (+Vref -Vref) in a
set of 2N reference voltages on chip, which are compared in parallel
with the analog input signal.
c
0
N
v
E
R
s
I
0
N
R
A
T
E
t
2N-1 2N-1
AMP CMP
Figure 2: Typical Flash ADC architecture