Alvin R. Lebeck

19 Pages·2016·0.2 MB·English

CURRICULUM VITAE
Alvin R. Lebeck

December 10, 2021

Department of Computer Science E-mail: [email protected]
D308 Levine Science Research Center Office phone: [phone]
Box 90129 Department phone: [phone]
Duke University Fax: [phone]
Durham, NC 27708-0129 URL: http://www.cs.duke.edu/~alvy

Employment History:
1. Professor, Department of Computer Science, Duke University, 2007—present.
2. Founder and Chairman of the Board, Phitonex, Inc. June 2018—Dec 2020.
3. Core Faculty, Innovation and Entrepreneurship, Duke University, 2019—present.
4. Founder and (acting) CEO, Phitonex, Inc. June 2017—June 2018.
5. Consulting Researcher, Microsoft Research, Jan 2013—June 2017.
6. Visiting Researcher, eXtreme Computing Group, Microsoft Research, Jul—Dec 2012.
7. Associate Professor, Department of Computer Science, Duke University, 2003—2007.
8. Assistant Professor, Department of Computer Science, Duke University, 1996—2002.
Education:
1. Ph.D. in Computer Science, University of Wisconsin at Madison, November 1995.
Advisor: Professor David A. Wood.
Thesis: Tools and Techniques for Memory System Design and Analysis.
2. Master of Science in Computer Science, University of Wisconsin at Madison, December 1991.
Advisor: Professor Gurindar S. Sohi.
Thesis: Request Combining in Multiprocessors with Arbitrary Interconnection Networks.
3. Bachelor of Science in Electrical and Computer Engineering (Dean’s honor list), University of
Wisconsin at Madison, May 1989.
Honors and Awards:
1. 2020 ACM SIGARCH Alan D. Berenbaum Distinguished Service Award.
2. IEEE Fellow 2017, “for contributions to memory hierarchies and energy-efficient and parallel
computing”
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3. Best paper awards:
a. 31st Annual ACM/IEEE International Symposium on Microarchitecture, November 1998.
b. 6th International Workshop on Network on Chip Architectures, December 2013.
4. IEEE MICRO Top Picks from Computer Architecture Conferences in 2009, 2010, 2017 honorable
mention.
5. NSF CAREER Award 1997.
6. Outstanding Graduate Student Researcher, Department of Computer Sciences, University of
Wisconsin—Madison, 1995.

Journal Publications:
1. Ramin Bashizade, Yuxuan Li, Alvin R. Lebeck, “Adaptive Simultaneous Multi-tenancy for GPUs,”
Proceedings of the 22nd Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP),
Springer, 2018.
2. Craig LaBoda, Chris Dwyer, Alvin R. Lebeck, “Exploiting Dark Fluorophore States to Implement
Resonance Energy Transfer Pre-Charge Logic”, in IEEE MICRO Special Issue on Post-Moore Computing,
July/August 2017.
3. Craig LaBoda, Alvin R. Lebeck, Chris Dwyer , “An Optically Modulated Self-Assembled Resonance
Energy Transfer Pass Gate”, Nano Letters, ACS Publications, 17(6), pp 3775-3781, 2017.
4. S. Yang, A. R. Lebeck, C. Dwyer, “Nanoscale Resonance Energy Transfer-based Devices for Probabilistic
Computing,” in IEEE Micro, Volume 35, Issue 5, pages 72-84, September/October 2015.
5. J. Pang, C. Dwyer, A. R. Lebeck, “mNoC: Large Nanophotonic Network-on-Chip Crossbars with
Molecular Scale Devices,” in ACM Journal on Emerging Technologies in Computing Systems (JETC),
Volume 12, Issue 1, pages 1-25, July 2015.
6. J. Pang, C. Dwyer, A. R. Lebeck, “Modeling and Simulation of a Nanoscale Optical Computing System,”
Journal of Parallel and Distributed Computing Special Issue on Nanoarchitectures, Volume 74, Issue 6,
pages 2470-2483, June 2014, available online August 2013.
7. B. F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin, “Address Translation-Aware Memory
Consistency,” in IEEE Micro Top Picks from Computer Architecture Conferences of 2010, Volume 31,
Issue 1, pages 109-118, January/February 2011.
8. M. Zhang, A. R. Lebeck, D. Sorin, “Fractal Consistency: Architecting the Memory System to Facilitate
Verification”, IEEE Computer Architecture Letters, Volume 9, Issue 2, pages 61-64, November 2010.
9. C. Pistol, V. Mao, A. R. Lebeck, C. Dwyer, “Encoded Multi-Chromophore Response for Simultaneous
Label-Free Detection,” in Small, Volume 6, No. 7, pages 843-850, April 9 2010.
10. Y. Liu, C. Dwyer, A. R. Lebeck, “Routing in Self-organizing Nano-scale Irregular Networks,” in ACM
Journal on Emerging Technologies in Computing Systems (JETC), Volume 6 , Issue 1, pages 1-
21, March 2010.
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11. C. Pistol, W. Chongchitmate, C. Dwyer, and A. R. Lebeck, “Architectural Implications of Nano-scale
Integrated Sensing and Computing,” in IEEE Micro Top Picks from Computer Architecture Conferences
of 2009, 30(1), pages 110-120, January/February 2010.
12. C. Pistol, C. Dwyer, A. R. Lebeck, “Nanoscale Optical Computing using Resonance Energy Transfer
Logic,” in IEEE Micro, 28 (6), pages 7-19 November/December 2008.
13. J. P. Patwardhan, C. Dwyer, A. R. Lebeck, “A Defect Tolerant Self-organizing Nanoscale SIMD
Architecture,” in ACM Journal on Emerging Technologies in Computing Systems (JETC), 3(2), July 2007.
14. T. Li, A. R. Lebeck, D. J. Sorin, “Spin Detection Hardware for Improved Management of Multithreaded
Systems,” in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 17(6), pages 508-521,
June 2006.
15. J. Patwardhan, C. Dwyer, A. R. Lebeck, D. J. Sorin, “NANA: A Nanoscale Active Network Architecture,”
in ACM Journal on Emerging Technologies in Computing Systems (ACM JETC), 2 (1), pages 1-30,
January 2006.
16. S. H. Park, C. Pistol, S. J. Ahn, J. H. Reif, A. R. Lebeck, C. Dwyer, T. H. LaBean, “Finite-size, Fully-
Addressable DNA Tile Lattices Formed by Hierarchical Assembly Procedures,” in Angewandte Chemie,
45(5), pages 735-739, January 23, 2006.
17. H. Zeng, C. S. Ellis, A. R. Lebeck, “Experiences in Managing Energy with ECOSystem,” in IEEE Pervasive
Computing, 4 (1), pages 62-68, January 2005.
18. C. Dwyer, A. R. Lebeck, D.J. Sorin, “Self-assembled Architecture and the Temporal Aspects of
Computing”, in IEEE Computer, 38 (1), pages 56-64, January 2005.
19. C. Yang, A. R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee “The Push Architecture: a Prefetching
Framework for Linked Data Structures,” in ACM Transactions on Architecture and Code Optimization
(ACM TACO), 1(4), pages 445 - 475, December 2004.
20. C. Dwyer, V. Johri, J. P. Patwardhan, A. R. Lebeck, and D. J. Sorin, “Design Tools for Self-assembling
Nanoscale Technology,” in Institute of Physics Nanotechnology, 15 (9) pages 1240-1245, September
2004.
21. M. Thottethodi, A. R. Lebeck, S. Mukherjee, “Exploiting Global Knowledge to Achieve Self-Tuned
Congestion Control for k-ary n-cube Networks,” in IEEE Transactions on Parallel and Distributed
Systems (IEEE TPDS), 15 (3), pages 257-272, March 2004.
22. S. Chatterjee, A. R. Lebeck, Praveen K. Patnala, M. Thottethodi, “Recursive Array Layouts and Fast
Parallel Matrix Multiplication,” in IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS),
13(11), pages 1105-1123, November 2002.
23. P. J. Hanlon, D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, and E. Parker, “The Combinatorics of
Cache Misses During Matrix Multiplication”, in Journal of Computer Sciences and Systems, 63(1). pages
80-126, August 2001.
24. C. Yang, B. Sano, and A. R. Lebeck, “Exploiting Parallelism in Geometry Processing with General
Purpose Processors and Floating-Point SIMD Instructions”, In IEEE Transactions on Computers, 49(9),
pages 934-946, September 2000.
25. S. T. Srinivasan and A. R. Lebeck, “Load Latency Tolerance in Dynamically Scheduled Processors”, In
the Journal on Instruction-Level Parallelism, vol. 1, November 1999 (http://www.jilp.org/vol1).
(Invited Paper)
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26. A. R. Lebeck and D. A. Wood, “Active Memory: A New Abstraction for Memory System Simulation,” In
ACM Transactions on Modeling and Computer Simulation (ACM TOMACS), 7(1), pages 42-77, January
1997.
27. A. R. Lebeck and D. A. Wood. “Cache Profiling and the SPEC Benchmarks: A Case Study,” IEEE
Computer, 27(10), pages 15–26, October 1994.
28. A. R. Lebeck and G. S. Sohi. “Request Combining in Multiprocessors with Arbitrary Interconnection
Networks,” IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), 5(11), pages 1140-1155,
November 1994.
29. D. A. Wood, S. Chandra, B. Falsafi, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, S. S. Mukherjee,
S. Palacharla, and S. K. Reinhardt. “Mechanisms for Cooperative Shared Memory”. In CMG
Transactions, Issue 84, Spring 1994, pages 51-62.
Books:
30. C. Dwyer and A. R. Lebeck, “Introduction to DNA Self-Assembled Computer Design”, ISBN-13 978-
1596931688, Artech House Publishers, January 2008.
Book Contributions:
31. C. Dwyer and A. R. Lebeck, “Self-Assembled Computer Architecture”. Systems Self-Assembly:
Multidisciplinary Snapshots, Natalio Krasnogor, Steve Gustafson, David Pelta and Jose L. Verdegay
(Eds.), ISBN-13: 978-0-444-52865-0, Elsevier, 2008.
32. I. Schoinas, B. Falsafi, A. R. Lebeck, S. K. Reinhardt, J. R. Larus, and D. A. Wood. “Fine-Grain Access
Control for Distributed Shared Memory”. Distributed Shared Memory: Concepts and Systems, by Jelica
Protic, Milo Tomaevic and Veljko Milutinovic, ISBN 0-8186-7737-6, IEEE Computer Society Press, 1997.
Refereed Conference and Symposia Publications:
33. J. Snyder, A. R. Lebeck, “Fast Convergence to Fairness for Reduced Long Flow Tail Latency in
Datacenter Networks,” in 36th IEEE International Parallel and Distributed Processing Symposium
(IPDPS), June 2022.
34. X. Zhang, R. Bashizade, Y. Wang, C. Lyu, S. Mukherjee and A. R. Lebeck, “Statistical Robustness of
Markov Chain Monte Carlo Accelerators,” in Proceedings of the Twenty Sixth International Conference
on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2021.
35. Ramin Bashizade, Xiangyu Zhang, Sayan Mukherjee, Alvin R. Lebeck, “EDGS: Optimizing Markov
Random Field Inference via Event-driven Gibbs Sampling.” In Semiconductor Research Corporation
Annual Technical Conference (TECHCON), September 2020.
36. Misra, P. A., M. F. Borge, I. Goiri, A. R. Lebeck, W. Zwaenepoel, and R. Bianchini. “Managing tail
latency in datacenter-scale file systems under production constraints.” In Proceedings of the 14th
Eurosys Conference 2019 (EuroSys ’19), Article 17, 2019.
37. Xiangyu Zhang, Ramin Bashizade, Craig D. LaBoda, Chris Dwyer, Alvin R. Lebeck, “Architecting a
Stochastic Computing Unit with Molecular Optical Devices”, Proceedings of the 43rd International
Symposium on Computer Architecture (ISCA), pages 301-314, June 2018.
38. Ali Razeen, Alvin R. Lebeck, David Liu, Alexander Meijer, Valentin Pistol, Landon P. Cox, “SandTrap:
Tracking Information Flows on Demand with Parallel Permissions,” Proceedings of the 16th ACM
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International Conference on Mobile Systems, Applications, and Services (MobiSys ‘18), pages 230-242,
June 2018.
39. Pulkit Misra, Jeffrey S. Chase, Johannes Gehrke, Alvin R. Lebeck, “Enabling Lightweight Transactions
with Precision Time,” in Proceedings of the Twenty Second International Conference on Architectural
Support for Programming Languages and Operating Systems (ASPLOS), pages 779-794, April 2017.
40. Siyang Wang, Xiangyu Zhang, Yuxuan Li, Ramin Bashizade, Song Yang, Chris Dwyer, Alvin R. Lebeck,
“Accelerating Markov Random Field Inference using Molecular Optical Gibbs Sampling Units,” in
Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), pages 558-569,
June 2016. (Also IEEE Top Picks Honorable Mention).
41. S. R. Agrawal, C. M. Dee, A. R. Lebeck, “Exploiting Accelerators for Efficient High Dimensional,” in
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
(PPoPP '16), March 2016.
42. J. Pang, C. Dwyer, A. R. Lebeck, “More is Less, Less is More: Molecular-Scale Photonic NoC Power
Topologies,” in Proceedings of the Twentieth International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS), pages 283-296, March 2015.
43. S. R. Agrawal, V. Pistol, J. Pang, J. Tran, D. Tarjan, A. R. Lebeck, “Rhythm: Harnessing Data Parallel
Hardware for Server Workloads,” in Proceedings of the Nineteenth International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 19-34,
March 2014.
44. Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin, “Fractal Coherence: Scalably Verifiable Cache
Coherence,” in Proceedings of the 43rd Annual IEEE/ACM International Symposium on
Microarchitecture, 2010 (MICRO 2010), pages 471-482, December 2010.
45. Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin, "Specifying and Dynamically Verifying
Address Translation-Aware Memory Consistency," in Proceedings of the Fifteenth International
Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS
’10), pages 323-334, March 2010.
46. Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, and Anne Bracy. "UNified
Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All," in 16th IEEE
International Symposium on High-Performance Computer Architecture, January 2010. (Also IEEE Top
Picks).
47. C. Pistol, W. Chongchitmate, C. Dwyer, and A. R. Lebeck, “Architectural Implications of Nano-scale
Integrated Sensing and Computing,” in Proceedings of the Fourteenth International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS ’09), pages 13-
24,March 2009. (Also IEEE Top Picks).
48. A. R. Lebeck, C. Dwyer, “Self-Organizing Defect Tolerant, Self-Assembled Nanoscale Architectures,” in
Nanoelectronic Devices for Defense and Security Conference, June 2007.
49. J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, “A Defect Tolerant Self-Organizing Nanoscale SIMD
Architecture,” in Proceedings of the Twelfth International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS XII), pages 241-251, October 2006. (25%
acceptance rate).
50. J. Patwardhan, C. Dwyer, A. R. Lebeck, “Self-Assembled Networks: Control vs. Complexity,” 1st
International Conference on Nano-Networks (NANONETS), September 2006
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51. C. Pistol, C. Dwyer, A. R. Lebeck, “Design Automation for DNA Self-Assembled Nanostructures,” in
Proceedings of the 43rd Design Automation Conference (DAC), July, 2006. (18% acceptance rate).
52. T. Li C. S. Ellis, A. R. Lebeck, D. J. Sorin, “Pulse: A Dynamic Deadlock Detection Mechanism using
Speculative Execution,” in Proceedings of USENIX Annual Technical Conference, April 2005. (20%
acceptance rate.)
53. J. P. Patwardhan, C. Dwyer, A. R. Lebeck, D. J. Sorin, “Circuit and System Architecture for DNA-Guided
Self-Assembly of Nanoelectronics,” in Proceedings of the Foundations of Nanoscience: Self-Assembled
Architectures and Devices (FNANO), April 2004. (Invited Paper)
54. J. Patwardhan, A. R. Lebeck, D. J. Sorin, “Communication Breakdown: Analyzing CPU usage in
Commercial Web Workloads,” in International Symposium on Performance Analysis of Systems and
Software (ISPASS '04), March 2004.
55. T. Li, A. R. Lebeck, D. J. Sorin, “Quantifying Instruction Criticality for Shared Memory Multiprocessors,”
in Proceedings of the International Symposium on Parallelism in Algorithms and Architectures (SPAA),
June 2003.
56. H. Zeng, C. S. Ellis, A. R. Lebeck, A. Vahdat, “Currentcy: A Unifying Abstraction for Expressing Energy
Management Policies,” in Proceedings of USENIX Annual Technical Conference, June 2003.
57. M. Thottethodi, A. R. Lebeck, S. Mukherjee, “BLAM: A High-Performance Routing Algorithm for Virtual
Cut-Through Networks,” in Proceedings of the International Parallel and Distributed Processing
Symposium (IPDPS), April 2003. (30% acceptance rate)
58. H. Zengh, C. S. Ellis, A. R. Lebeck, A. Vahdat, “ECOSystem: Managing Energy as a First Class Operating
System Resource,” in Proceedings of the Tenth International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS X), pages 123-132, October 2002. (18%
acceptance rate)
59. A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, E. Rotenberg, “A Large, Fast Instruction Window for
Tolerating Cache Misses,” in Proceedings of the 29th International Symposium on Computer
Architecture (ISCA), pages 59-70, May 2002. (15% acceptance rate)
60. C. Yang and A. R. Lebeck, “A Programmable Memory Hierarchy for Prefetching Linked Data
Structures,” in Proceedings of the 4th International Symposium on High Performance Computing
(ISHPC-IV), G. Goos, J. Hartmanis, and J. van Leeuwen Eds. Springer Lecture Notes in Computer
Science, vol. 2327, May 2002.
61. X. Fan, C. S. Ellis, A. R. Lebeck, “Memory Controller Policies for DRAM Power Management,” in
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pages 129-
134, August, 2001. (13% acceptance rate)
62. S. T. Srinivasan, C. Wilkerson, R. Ju, and A. R. Lebeck, “Locality vs. Criticality,” in Proceedings of the
28th International Symposium on Computer Architecture (ISCA), pages 132-143, June 2001. (15%
acceptance rate)
63. S. Chatterjee, E. Parker, P. Hanlon, A. R. Lebeck, “Exact Analysis of the Cache Behavior of Nested
Loops,” in Proceedings of the International Symposium on Programming Language Design and
Implementation (PLDI), pages 286-297, June 2001. (20% acceptance rate)
64. M. Thottethodi, A. R. Lebeck, S. Mukherjee, “Self-tuned Congestion Control for Multiprocessor
Networks,” in Proceedings of the Seventh International Symposium on High Performance Computer
Architecture (HPCA-7), pages 107-118, January 2001. (23% acceptance rate)
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65. A. R. Lebeck, X. Fan, H. Zengh, C. S. Ellis, “Power Aware Page Allocation,” in Proceedings of the Ninth
International Conference on Architectural Support for Programming Languages and Operating
Systems (ASPLOS IX), pages 105-116, November 2000. (21% acceptance rate)
66. A. Vahdat, A. R. Lebeck, C. S. Ellis, “Every Joule is Precious: The Case for Revisiting Operating System
Design for Energy Efficiency,” in ACM SIGOPS European Workshop, September 2000.
67. C. Yang and A. R. Lebeck, “Push vs. Pull: Data Movement for Linked Data Structures,” in Proceedings of
the 14th ACM International Conference on Supercomputing, pages 176-186, May 2000. (26%
acceptance rate)
68. J. S. Chase, D. C. Anderson, A. J. Gallatin, A. R. Lebeck, and K. G. Yocum, “Network I/O with Trapeze,”
in IEEE Hot Interconnects, August 1999. (Invited Paper)
69. A. R. Lebeck, D. R. Raymond, M. S. Thottethodi, and C. Yang, “Annotated Memory References: A
Mechanism for Informed Cache Management,” in Proceedings of the 5th International Euro-Par
Conference, Lecture Notes in Computer Science 1685, P. Amestoy et al. (Editors), Springer-Verlag,
pages 1251-1254, August 1999. (54% acceptance rate)
70. S. Chatterjee, A. R. Lebeck, Praveen K. Patnala, M. Thottethodi, “Recursive Array Layouts and Fast
Parallel Matrix Multiplication,” in Proceedings of the 11th ACM Symposium on Parallel Algorithms and
Architectures (SPAA), pages 222-231, June 1999. (29% acceptance rate)
71. S. Chatterjee, V. Jain, A. R. Lebeck, S. Mundhra, M. Thottethodi, “Nonlinear Array Layouts for
Hierarchical Memory Systems,” in Proceedings of the 13th ACM International Conference on
Supercomputing, pages 444-453, June 1999. (28% acceptance rate)
72. A. R. Lebeck, “Cache Conscious Programming in Undergraduate Computer Science,” in Proceedings of
the 30th SIGCSE Technical Symposium on Computer Science Education, pages 247-251, March 1999.
(39% acceptance rate)
73. S. T. Srinivasan and A. R. Lebeck, “ Load Latency Tolerance in Dynamically Scheduled Processors,” in
Proceedings of the 31st Annual International Symposium on Microarchitecture (MICRO), pages 148-
159, November 1998. (Best paper award, 26% acceptance rate)
74. C. Yang, B. Sano, and A. R. Lebeck, “Exploiting Instruction Level Parallelism in Geometry Processing for
Three Dimensional Graphics Applications,” in Proceedings of the 31st Annual International Symposium
on Microarchitecture (MICRO), pages 14-24, November 1998. (26% acceptance rate)
75. M. S. Thottethodi, S. Chatterjee, and A. R. Lebeck, “Tuning Strassen’s Matrix Multiplication for
Memory Efficiency,” in Proceedings of Supercomputing 98, November 1998. (Best student paper
finalist, 25% acceptance rate)
76. V. P. Pauca, X. Sun, S. Chatterjee, and A. R. Lebeck, “Architecture-Efficient Strassen’s Matrix
Multiplication: A Case Study of Divide-and-Conquer Algorithms,” in International Linear Algebra
Society (ILAS) Symposium on Algorithms for Control, Singles, and Image Processing, June 1997.
77. K. Yocum, J. Chase, A. Gallatin, and A. R. Lebeck, “Cut-Through Delivery in Trapeze: An Exercise in Low-
Latency Messaging,” in Proceedings of the IEEE International Conference on High Performance
Distributed Computing (HPDC) August 1997. (47% acceptance rate)
78. A. R. Lebeck and D. A. Wood, “Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-
Memory Multiprocessors,” in Proceedings of the 22nd Annual International Symposium on Computer
Architecture (ISCA), pages 48-59, June 1995. (20.5% acceptance rate)
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79. A. R. Lebeck and D. A. Wood, “Active Memory: A New Abstraction for Memory System Simulation,” in
Proceedings of the 1995 ACM Sigmetrics Conference on Measurement and Modeling of Computer
Systems, pages 220-230, May 1995. (21.9% acceptance rate)
80. I. Schoinas, B. Falsafi, A. R. Lebeck, S. K. Reinhardt, J. R. Larus, and D. A. Wood, “Fine-Grain Access
Control for Distributed Shared Memory,” in Proceedings of the Sixth International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), pages 297-
306, October 1994. (19.9% acceptance rate)
81. B. Falsafi, A. R. Lebeck, S. K. Reinhardt, I. Schoinas, M. D. Hill, J. R. Larus, A. Rogers, and D. A. Wood,
“Application-Specific Protocols for User-Level Shared Memory,” in Proceedings of Supercomputing 94,
pages 380-389, November 1994.
82. S. K. Reinhardt, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, and D. A. Wood, “The Wisconsin Wind
Tunnel: Virtual Prototyping of Parallel Computers,” in Proceedings of the 1993 ACM Sigmetrics
Conference on Measurement and Modeling of Computer Systems, pages 48–60, May 1993.
83. D. A. Wood, S. Chandra, B. Falsafi, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, S. S. Mukherjee,
S. Palacharla, and S. K. Reinhardt, “Mechanisms for Cooperative Shared Memory,” in Proceedings of
the 20th Annual International Symposium on Computer Architecture (ISCA), pages 156–167, May 1993.
(15.7% acceptance rate)
84. R. E. Kessler, R. J. Jooss, A. R. Lebeck, and M. D. Hill, “Inexpensive Implementations of Set-
Associativity,” in Proceedings of the 16th Annual International Symposium on Computer Architecture
(ISCA), pages 131–139, June 1989. (27% acceptance rate)
Refereed Workshop Publications:
85. J. Snyder, D. Zhou, A. R. Lebeck, “RDMA Congestion Control: It’s Only for the Compliant”, in
Cloud@MICRO 2021, Oct 2021.
86. Ramin Bashizade, Xiangyu Zhang, Sayan Mukherjee, Alvin R. Lebeck, “Optimizing Markov Random
Field Inference via Event-Driven Gibbs Sampling on GPUs,” COGARCH 2021, Fifth Workshop on
Cognitive Architectures, February 2021.
87. X. Zhang, R. Bashizade, Y. Wang, C. Lyu, S. Mukherjee and A. R. Lebeck, “Statistical Robustness of
MCMC Accelerators,” in 2nd Workshop on Accelerated Machine Learning (AccML), May 2020.
88. Ramin Bashizade, Yuxuan Li, Alvin R. Lebeck, “Adaptive Simultaneous Multi-tenancy for GPUs,”
Proceedings of the 22nd Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP 2018),
May 2018.
89. J. Pang, C. Dwyer A. R. Lebeck, “Exploiting Emerging Technologies for Nanoscale Photonic Networks-
on-Chip,” in Sixth International Workshop on Network on Chip Architectures (NoCArc-13), December
2013. Best Paper Award
90. Y. Liu, A. R. Lebeck, “Nano-scale On-chip Irregular Network Analysis,” Proceedings of ICCCN 09
Workshop on Nano Molecular and Quantum Information Networks (NanoCom), August 2009.
91. C. Dwyer, A. R. Lebeck, C. Pistol, “Energy Transfer Logic on DNA Nanostructures: Enabling Molecular-
Scale Amorphous Computing,” in Proceedings of the 4th Workshop on Non-Silicon Computing, pages
33-40, June 2007.
92. A. R. Lebeck, and C. Dwyer, “Self-Organizing, Defect Tolerant, Self-Assembled Nanoscale
Architectures,” in Nanoelectronic Devices for Defense and Security, June 2007.
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93. J. Patwardhan, C. Dwyer, A. R. Lebeck, “Design and Evaluation of Fail-Stop Self-Assembled Nanoscale
Processing Elements,” in IEEE International Workshop on Design and Test of Defect-Tolerant
Nanoscale Architectures (NANOARCH ’06), June 2006.
94. Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin, “Evaluating the Connectivity of
Self-Assembled Networks of Nano-scale Processing Elements,” in IEEE International Workshop on
Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH ’05), May 2005.
95. X. Fan, C. S. Ellis, A. R. Lebeck, “The Synergy between Power-aware Memory Systems and Processor
Voltage Scaling,” in Proceedings of the Workshop on Power Aware Computing Systems 2003 (PACS
’03), Springer-Verlag Lecture Notes in Computer Science, vol. 2325, pages 164-179, December 2003.
96. X. Fan, C. S. Ellis, A. R. Lebeck, “Modeling of DRAM Power Control Policies Using Deterministic and
Stochastic Petri Nets,” in Proceedings of the Workshop on Power Aware Computing Systems 2002
(PACS ’02), Springer-Verlag Lecture Notes in Computer Science,vol. 3164, pages 130-140, February
2002.
97. D. Genius, S. Chatterjee, and A. R. Lebeck, “Array Merging: A Technique for Improving Cache and TLB
Behavior,” in Workshop on Memory Performance Issues, in conjunction with International Symposium
on Computer Architecture, June 2001.
Poster Presentations & Other Works:
98. C. Kjellqvist, L. Wills, A. R. Lebeck, “A Case for Down-Scaled Burn-In for MCMC Accelerators”, 2021
IBM/IEEE AI Compute Symposium (AICS), October 2021.
99. Xiangyu Zhang, Sayan Mukherjee, Alvin R. Lebeck, “A Case for Quantifying Statistical Robustness of
Specialized Probabilistic AI Accelerators,” in 2019 IBM IEEE CAS/EDS – AI Compute Symposium,
October 2019 (also arXiv:1910.12346).
100. S. R. Agrawal, A. R. Lebeck, “Cost-Efficient Cluster Design for High Dimensional Similarity Search,” in
GPU Technology Conference, March 2015.
101. S. R. Agrawal, V. Pistol, J. Pang, J. Tran, D. Tarjan, A. R. Lebeck, “Rhythm: Harnessing Data Parallel
Hardware for Server Workloads,” in GPU Technology Conference, March 2014.
102. J. Pang, C. Dwyer, A. R. Lebeck, “mNoC: Large Nanophotonic Network-on-Chip Crossbars with
Molecular Scale Devices,” General Poster Session at Grace Hopper Celebration, October 2013.
103. S. R. Agrawal, V. Pistol, J. Pang, J. Tran, A. R. Lebeck, “Leveraging GPUs for High Throughput Web
Servers,” GPU Technology Conference, March 2013.
104. J. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, “A Defect Tolerant Self-organizing Nanoscale SIMD
Architecture,” in Workshop on Edge Computing Using New Commodity Architectures (EDGE), May
2006.
105. C. Dwyer, S. H. Park, T. LaBean, A. R. Lebeck, “The Design and Fabrication of a Fully Addressable 8-tile
DNA Lattice,” Proceedings of the Foundations of Nanoscience: Self-Assembled Architectures and
Devices (FNANO), April 2005
106. J. Patwardhan, C. Dwyer, A. R. Lebeck, D. J. Sorin, NANA: A Nanoscale Active Network Architecture, in
Proceedings of the Foundations of Nanoscience: Self-Assembled Architectures and Devices (FNANO),
April 2004.
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107. C. Dwyer, V. Johri, M. Cheung, J. P. Patwardhan, A. R. Lebeck, and D. J. Sorin, CAD Support for DNA-
Guided Self-Assembly of Nanoelectronics, in Proceedings of the Foundations of Nanoscience: Self-
Assembled Architectures and Devices (FNANO), April 2004.
108. H Zengh, C. S. Ellis, X. Fan, A. R. Lebeck, A.Vahdat, “ECOSystem: Managing Energy as a First Class
Operating System Resource,” ACM International Symposium on Operating Systems Principles (SOSP),
poster session workshop, October 2001.
Technical Reports:
1. R. Bashizade, X. Zhang, S. Mukherjee, A. R. Lebeck, “Accelerating Markov Random Field Inference with
Uncertainty Quantification,” arXiv:2108.00570, August 2021.
2. X. Zhang, R. Bashizade, Y. Wang, C. Lyu, S. Mukherjee and A. R. Lebeck, “Beyond Application End-Point
Results: Quantifying Statistical Robustness of MCMC Accelerators,” arXiv:abs/2003.04223, March
2020.
3. Pulkit A. Misra, Srihari Radhakrishnan, Jeffrey S. Chase, Johannes Gehrke, Alvin R. Lebeck,
“Lightweight Inter-transaction Caching with Precise Clocks and Dynamic Self-invalidation,”
arXiv:2003.04150, March 2020.
4. Multi-version Indexing in Flash-based Key-Value Stores. Pulkit Misra, Jeffrey S. Chase, Johannes
Gehrke, Alvin R. Lebeck, arXiv:1912.00580, Dec 2019.
5. Yang Liu, Chris Dwyer, Alvin R. Lebeck, Combined Compute and Storage: Configurable Memristor
Arrays to Accelerate Search, arXiv:1601.05273, Jan 2016.
6. Jun Pang, Chris Dwyer, Alvin R. Lebeck, “mNoC: Large Nanophotonic Network-on-Chip Crossbars with
Molecular Scale Devices,” Technical Report CS-2013-02, Department of Computer Science, Duke
University, 2013.
7. J. P. Patwardhan, C. Dwyer, A. R. Lebeck, and D. J. Sorin, NANA: A Nano-scale Active Network
Architecture, Duke University Computer Science Department Technical Report, 2003.
8. T. Li, A. R. Lebeck, D. J. Sorin, “Spin Detection Hardware for Management of Multithreaded Systems,”
Duke University Computer Science Department Technical Report, 2004.
9. H. Zeng, C. Ellis, A. Lebeck, A. Vahdat, “Currentcy: Unifying Policies for Resource Management,” Duke
University Computer Science Technical Report CS-2002-09, May 2002.
10. T. Li, J. Koppanalil, A. R. Lebeck, J. Patwardhan, E. Rotenberg, “A Large, Fast Instruction Window for
Tolerating Cache Misses,” Duke University Computer Science Technical Report CS-2002-03 March
2002.
11. M. Thottethodi, A. R. Lebeck, S. Mukherjee, “Key Components of High-Performance Routing
Algorithms for Virtual Cut-Through Networks,” Duke University Computer Science Technical Report
CS-2002-02, Jan 2002.
12. H Zengh, C. S. Ellis, X. Fan, A. R. Lebeck, A.Vahdat, “ECOSystem: Managing Energy as a First Class
Operating System Resource,” Duke University Computer Science Technical Report CS-2001-01, April
2001.
13. M. Thottethodi, A. R. Lebeck, S. Mukherjee, “Self-tuned Congestion Control for Multiprocessor
Networks,” Duke University Computer Science Technical Report CS-2000-15, November 2000.
Lebeck CV Page 10