Advanced verification techniques : a systemC based approach for successful tapeout

388 Pages·2004·13.787 MB·English

by  Leena Singh, Leonard Drucker, Neyaz Khann

ADVANCED VERIFICATION
TECHNIQUES:
A SystemC Based Approach for
Successful Tapeout
ADVANCED VERIFICATION
TECHNIQUES:
A SystemC Based Approach for
Successful Tapeout
by
Leena Singh
Azanda Network Devices
Leonard Drucker
Cadence Design Systems
Neyaz Khan
Cadence Design Systems Inc.
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 1-4020-8029-8
Print ISBN: 1-4020-7672-X
©2004 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2004 Kluwer Academic Publishers
Boston
All rights reserved
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Created in the United States of America
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Contents
Authors xi
Acknowledgements xiii
Foreword xv
CHAPTER 1 Introduction 1
l.l Verification Overview and Challenges 3
1.1.1 Challenges 5
1.2Topics Covered in the book 7
1.2.1 Introduction 7
1.2.2Verification Process 7
1.2.3 Using SCV for Verification 7
1.2.4 Test Plan 7
1.2.5Test Bench Concepts using SystemC 8
1.2.6Methodology 8
1.2.7Regression 8
1.2.8Functional Coverage 9
1.2.9Dynamic Memory Modeling 9
1.2.10Post Synthesis/Gate Level Simulation 9
1.3Reference Design 10
1.3.1 Networking Traffic Management and SAR chip 10
1.3.2 Multimedia Reference Design 14
CHAPTER 2 Verification Process 17
2.1 Introduction 18
2.2Lint 21
2.3High Level verification languages 22
2.4Documentation 26
2.4.1 Documenting verification infrastructure 27
2.5 Scripting 30
2.6Revision control 32
2.7Build Process 35
2.8 Simulation and waveform analysis 35
2.8.1 Waveform Analysis tool features 36
2.9Bug tracking 37
2.10Memory modelling 39
2.11 Regression 40
2.12 Functional Coverage 40
2.12.1 Requirements for a Functional Coverage Tools 40
2.12.2Limitations of Functional Coverage 41
vi Advanced Verification Techniques
2.13 Code Coverage 41
CHAPTER 3 Using SCV for Verification 45
3.1Features a verification language 45
3.2Why use C++ for SCV? 47
3.3What is randomization 48
3.4 Introduction to SCV 49
3.4.1 Basic Purpose of SCV 49
3.4.2 Basic Language Constructs of SCV 50
3.4.3 Examples of an SCV testbench 53
3.5Creating A Stimulus Generator using SCV 54
3.5.1 Testbench Structure 54
3.5.2 Randomization 56
3.6Future of SCV 64
CHAPTER 4 Functional Verification Testplan 65
4.1 Different kinds of Tests 66
4.2When to Start 68
4.3Verification plan document 70
4.4 Purpose and Overview 70
4.4.1 Intended Use 70
4.4.2 Project References 70
4.4.3 Goals 70
4.4.4 System Level Testbench: 72
4.4.5 DUV 73
4.4.6 Transaction Verification Modules 74
4.4.7 Packet/Cell Generators 75
4.4.8 CPU Command Generators 76
4.4.9 Packet/Cell Checkers 76
4.4.10 System Level Checker 77
4.4.11 Rate Monitors 77
4.4.12 Simulation Infrastructure 78
4.4.13 Verification Infrastructure 80
4.4.14 System Testing 83
4.4.15 Basic Sanity Testing 83
4.4.16 Memory and Register Diagnostics 83
4.4.17 Application types sanity tests 84
4.4.18 Data path Verification 84
4.4.19 Chip Capacity Tests 85
4.4.20 Framer Model 86
4.4.21Congestion Check 86
4.4.22 Customer Applications 86
4.4.23 FreeBuffer List checking 86
Contents vii
4.4.24 Overflow FIFOs 86
4.4.25 Backpressure 86
4.4.26 Negative Tests 86
4.4.27 Block Interface Testing 87
4.4.28 Chip feature testing 87
4.4.29 Random Verification 89
4.4.30 Corner Case Verification 90
4.4.31Protocol Compliance checking 90
4.4.32 Testing not done in simulation 90
4.4.33 Test Execution Strategy 90
4.5Tests Status/Description document 91
4.6Summary 93
CHAPTER 5 Testbench Concepts using SystemC 95
5.1 Introduction 95
5.1.1Modeling Methods 95
5.1.2TransactionLevelModeling 96
5.1.3 Block level Verification using TLM 97
5.2Unified Verification Methodology(UVM). 103
5.2.1 Functional Virtual Prototype 104
5.2.2Transactions 107
5.2.3 Assertions 109
5.2.4Considerations in creating an FVP 110
5.2.5Creating the FVP 113
5.3Testbench Components 117
5.3.1Verification Communication Modes 119
5.3.2Using Transactions in testbenches 123
5.3.3 Characteristics of Transactions 124
5.3.4Hierarchical Transactions 125
5.3.5 Related Transactions in multiple streams 125
CHAPTER 6 Verification Methodology 149
6.1Introduction 150
6.2Overall Verification approach 150
6.3What all tools are needed 152
6.4Transactionbased verification environment: 153
6.4.1 Elements of TBV 154
6.5Designverification 155
6.5.1 System Level Verification 156
6.5.2 Block Level Verification 159
6.5.3 Block TVMs at system level: Interface TVMs: 160
6.6Verification infrastructure 161
6.7Interface TVMs 162
viii Advanced Verification Techniques
6.7.1 PL3 163
6.7.2 Other interfaces 170
6.8Traffic Generation 170
6.8.1Traffic generator methodology 170
6.8.2Overall Flow 172
6.8.3 Implementation flow 174
6.8.4 Interface Driver hookup to traffic Generation 175
6.8.5 To setup test stimulus for generation: 176
6.9Writing Stimulus File 177
6.9.1 Example stimulus file front end 177
6.10 Monitors 193
6.11 Checkers 193
6.11.1Methodology used in reference design 194
6.12 Message Responder 201
6.12.1Flow 201
6.12.2Basic Structure 203
6.12.3Example code 203
6.13Memory models 209
6.14Top Level simulation environment 209
6.15Results of using well defined methodology 210
CHAPTER 7 Regression/Setup and Run 211
7.1Goals of Regression 212
7.2Regression Flow and Phases 213
7.2.1 Regression Phases 214
7.3Regression Components 216
7.3.1 Bug tracking 216
7.3.2 Hardware 217
7.3.3 Host Resources 217
7.3.4 Load Sharing Software 218
7.3.5 Regression Scripts 219
7.3.6 Regression Test Generation 219
7.3.7 Version control 220
7.4 Regression features 220
7.4.1 Important features for regression 220
7.4.2 Common switches for Regression 224
7.5Reporting Mechanism 225
7.5.1 Pass/fail count Report 226
7.5.2 Summary for each test case 227
7.5.3 Verbose Report for Debugging if error occurs 227
7.5.4 Error diagnosis 227
7.5.5 Exit criteria 227
Contents ix
7.5.6 Verification Metrics 228
7.6Common Dilemmas in Regression 228
7.7 Example of Regression run 229
7.7.1 Run options. 229
7.8Summary 231
CHAPTER 8 Functional Coverage 233
8.1Use of Functional Coverage. 234
8.1.1Basic Definition FunctionalCoverage. 234
8.1.2 Why Use a Functional Coverage? 234
8.2Using Functional Coverage in Verification environment. 236
8.2.1Functional and Code Coverage Difference. 236
8.3Implementation and Examples of Functional Coverage. 237
8.3.1Coverage Model Design. 238
8.3.2 Transaction Functional Coverage techniques. 241
8.3.3 Functional Coverage Examples 243
8.3.4 Role of Functional and Code coverage 245
8.4 Functional Coverage Tools. 245
8.4.1 Commercial Functional Coverage Tools. 245
8.4.2 Features of a good functional coverage tool. 246
8.4.3Requirements for a Functional CoverageTools 248
8.5Limitationsof Functional Coverage 250
CHAPTER 9 Dynamic Memory Modeling 251
9.1Various solutions for simulation memory models 252
9.2Running simulation with memory models 252
9.2.1 Built in memory models 252
9.3Buying commercially available solutions 255
9.4Comparing Built in and Commercial memory models 256
9.5Dynamic Memorymodeling Techniques 260
9.5.1 Verilog 261
9.5.2 Using Wrapper 262
9.6Example From Reference Design: 264
9.6.1 Performance comparison 273
CHAPTER 10 Post Synthesis Gate Simulation 275
10.1Introduction 276
10.1.1Need for Gate Level Simulation 276
10.2Different models for running gatenetlist simulation 277
10.2.1Gate Simulation with Unit Delay timing 277
10.2.2Gate-level simulation with full timing 277
10.3Different types of Simulation 278
10.3.1 Stages for simulation in design flow 280
10.4 Getting ready for gate simulation 281
x Advanced Verification Techniques
10.4.1 Stimulus generation 281
10.4.2 Backannotating SDF files 282
10.4.3 Multicycle path 282
10.4.4 Using Sync Flops 283
10.4.5ncpulse and transport delays 284
10.4.6 Pulsehandling by simulator 285
10.5 Setting up the gate level simulation 287
10.6ATE vector Generation 289
10.6.1 Requirement for Functional testing on ATE 289
10.6.2 Various ATE Stages 290
10.6.3 Choosingfunctional simulations for ATE 290
10.6.4Generating vectors 291
10.6.5 Applying vectors back to netlist 291
10.6.6 Testing at ATE 291
10.6.7 Problem at speed vectors 292
10.7 Setting up simulation for ATE vector generation 293
10.8 Examples of issues uncovered by gate simulations 294
APPENDIX 297
0.1CommonInfrastructure 297
0.2Simple example based on above methodology 299
0.2.1 Generator 299
0.2.2 Sideband 303
0.2.3 Driver 304
0.2.4 Monitor 310
0.2.5 Checker 314
0.2.6 Stim 318
0.2.7 SimpleRasTest.h 318
0.2.8 SimpleRasTest.cc 318
0.3Example for standard interfaces: 319
0.3.1 Code Example for PL3Tx Standard interface: 319
0.3.2 Code Example for Standard PL3Rx interface 332
0.3.3 SPI4 interface 338
0.3.4 Code Example for SPI4 interface 344
References 371
Index. 373