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SpringerSeries in ADVANCED MICROELECTRONICS 34 SpringerSeriesin ADVANCED MICROELECTRONICS SeriesEditors:K.Itoh T.H.Lee T.Sakurai W.M.C.Sansen D.Schmitt-Landsiedel The Springer Series in Advanced Microelectronics provides systematic information on all thetopicsrelevantforthedesign,processing,andmanufacturingofmicroelectronicdevices. Thebooks,eachpreparedbyleadingresearchersorengineersintheirfields,coverthebasic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series formsabridgebetweenphysicsandengineeringandthevolumeswillappealtopracticing engineersaswellasresearchscientists. Forfurthervolumes: www.springer.com/series/4076 Philip Teichmann Adiabatic Logic Future Trend and System Level Perspective Dr.-Ing.PhilipTeichmann LehrstuhlfürTechnischeElektronik TechnischeUniversitätMünchen Arcisstrasse21 80333Munich Germany [email protected] SeriesEditors: Dr.KiyooItoh HitachiLtd.,CentralResearchLaboratory,1-280Higashi-Koigakubo,Kokubunji-shi,Tokyo 185-8601,Japan ProfessorThomasH.Lee Department of Electrical Engineering, Stanford University, 420 Via Palou Mall, CIS-205 Stanford,CA94305-4070,USA ProfessorTakayasuSakurai CenterforCollaborativeResearch,UniversityofTokyo,7-22-1Roppongi,Minato-ku,Tokyo 106-8558,Japan ProfessorWillyM.C.Sansen ESAT-MICAS, Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, 3001 Leuven, Belgium ProfessorDorisSchmitt-Landsiedel LehrstuhlfürTechnischeElektronik,TechnischeUniversitätMünchen,Theresienstrasse90, GebäudeN3,80290Munich,Germany ISSN1437-0387 SpringerSeriesinAdvancedMicroelectronics ISBN978-94-007-2344-3 e-ISBN978-94-007-2345-0 DOI10.1007/978-94-007-2345-0 SpringerDordrechtHeidelbergLondonNewYork LibraryofCongressControlNumber:2011941857 ©SpringerScience+BusinessMediaB.V.2012 Nopartofthisworkmaybereproduced,storedinaretrievalsystem,ortransmittedinanyformorby anymeans,electronic,mechanical,photocopying,microfilming,recordingorotherwise,withoutwritten permissionfromthePublisher,withtheexceptionofanymaterialsuppliedspecificallyforthepurpose ofbeingenteredandexecutedonacomputersystem,forexclusiveusebythepurchaserofthework. Coverdesign:VTeXUAB,Lithuania Printedonacid-freepaper SpringerispartofSpringerScience+BusinessMedia(www.springer.com) Preface Adiabatic Logic is a potential successor for static CMOS circuit design when it comestoultra-low-powerenergyconsumption.Futuredevelopmentliketheevolu- tionaryshrinkingoftheminimumfeaturesizeaswellasrevolutionarynoveltransis- torconceptswillchangethegatelevelsavingsgainedbyAdiabaticLogic.Inaddi- tion,theimpactofworseningdegradationeffectshastobeconsideredinthedesign ofadiabaticcircuits.Theimpactofthetechnologytrendsonthefiguresofmeritof AdiabaticLogic,energysavingpotentialandoptimumoperatingfrequency,arein- vestigated,aswellasdegradationrelatedissues.Adiabaticlogicbenefitsfromfuture devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias TemperatureInstabilitythanstaticCMOScircuits.Majorinterestalsoliesontheef- ficientgenerationoftheappliedpower-clocksignal.Thisoscillatingpowersupply canbeusedtosaveenergyinshortidletimesbydisconnectingcircuits.Anefficient way to generate the power-clock is by means of the synchronous 2N2P LC oscil- lator,whichisalsorobustwithrespecttopattern-inducedcapacitivevariations.An easytoimplementbutpowerfulPower-ClockGatingsupplementisproposedbygat- ingthesynchronizationsignals.Diverseimplementationstoshutdownthesystem are presented and rated for their applicabilityand other aspects like energy reduc- tioncapabilityanddataretention.AdvantageoususageofAdiabaticLogicrequires compactandefficientarithmeticstructures.Abroadvarietyofadderstructuresanda CoordinateRotationDigitalComputerarecomparedandratedaccordingtoenergy consumptionandareausage,andtheresultingenergysavingpotentialagainststatic CMOSprovestheultra-low-powercapabilityofAdiabaticLogic.Intheend,anew circuittopologyhastocompetewithstaticCMOSalsoinproductivity.Ona130nm testchip,alargescaletestvehiclecontaininganFIRfilterwasimplementedinAdi- abatic Logic, utilizing a standard, library-based design flow, fabricated, measured andcomparedtosimulationsofastaticCMOScounterpart,withmeasuredsaving factors compliant to the values gained by simulation. This leads to the conclusion thatAdiabaticLogicisreadyforproductivedesignduetocompatibilitynotonlyto CMOStechnology,butalsotoelectronicdesignautomation(EDA)toolsdeveloped forstaticCMOSsystemdesign. Munich,Germany PhilipTeichmann v Acknowledgements Presenteddatainthisworkisaresultofmyemploymentasaresearchassistantatthe LehrstuhlfürTechnischeElektronik(LTE)attheTechnischeUniverstitätMünchen. PhDthesesattheLTEdealingwithAdiabaticLogicwerepublishedbyEttoreAmi- rante and Jürgen Fischer previously. Ettore and Jürgen have supplied the basis for my work on Adiabatic Logic. Jürgen was my roommate for a couple of years and wehadmanyfruitfuldiscussions. The opportunity to work at the LTE was offered to me by my supervisor and head of the institute, Professor Doris Schmitt-Landsiedel. She supported the work onAdiabaticLogicwithalotofenlighteninginputandpersonaleffort.Iwouldlike to thank her for giving me the chance to be a part of the team at LTE. I always enjoyed being a member of a team that is composed of committed and inspiring people. A lot of input has come from the colleagues working on diverse fields of researchattheinstitute. FurthermoreIwanttousetheopportunitytothankmyparentsfortheirsupport andtheirpatiencealongthislongacademicjourney.Veronika,youmanagedtokeep memotivatedduringalmostallstagesofthiswork. The Deutsche Forschungsgemeinschaft(DFG) supported the research on Adia- baticLogicintheSchwerpunktprogrammVIVA.WithintheVIVAprojectIworked togetherwithProf.JürgenGötzefromtheTechnischeUniversitätDortmund.Prof. JürgenGötzeconfirmedtobethesecondsupervisorofthisthesis,Iamverygrateful forhiseffort. PhilipTeichmann vii Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 MotivationforThisWork . . . . . . . . . . . . . . . . . . . . . . 1 1.2 ABriefHistoryofReversibleComputationandAdiabatic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 FundamentalsofAdiabaticLogic . . . . . . . . . . . . . . . . . . . . 5 2.1 TheChargingProcessinAdiabaticLogicCompared toStaticCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 TheDefinitionoftheEnergySavingFactor(ESF) . . . . . 8 2.2 AnAdiabaticSystem . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 IntroducingAdiabaticLogicFamiliesUsedinThisWork . 8 2.2.2 TheFour-PhasePower-Clock . . . . . . . . . . . . . . . . 9 2.3 LossMechanismsinAdiabaticLogic . . . . . . . . . . . . . . . . 10 2.3.1 ImpactofProcessVariationsontheLossesinAdiabatic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 VoltageScaling—AComparisonofStaticCMOSandAdiabatic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 PropertiesofAdiabaticLogicandResultantDesignConsiderations 15 2.5.1 Dual-RailEncodedSignals . . . . . . . . . . . . . . . . . 15 2.5.2 InherentPipelining. . . . . . . . . . . . . . . . . . . . . . 17 2.5.3 DelayConsiderationsinAdiabaticLogic . . . . . . . . . . 18 2.5.4 ThePowerSupplyNetinAdiabaticLogic:Crosstalk, iR-drop,Ldi-drop,Electromigration . . . . . . . . . . . . 18 dt 2.6 GeneralSimulationSetup . . . . . . . . . . . . . . . . . . . . . . 21 3 FutureTrendinAdiabaticLogic . . . . . . . . . . . . . . . . . . . . 23 3.1 ScalingTrendsforSub90nmTransistors . . . . . . . . . . . . . . 24 3.2 AdiabaticLogicwithNovelDevices . . . . . . . . . . . . . . . . 30 3.2.1 WhatShouldanIdeal(Novel)DeviceforAdiabaticLogic LookLike? . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.2 AdiabaticLogicwithCarbonNanotubes(CNT) . . . . . . 36 ix x Contents 3.2.3 Adiabatic Logic with the Vertical Slit Field Effect Transistor(VESFET) . . . . . . . . . . . . . . . . . . . . 43 3.3 (Negative)BiasTemperatureInstability((N)BTI)andHotCarrier Injection(HCI)inAdiabaticLogic . . . . . . . . . . . . . . . . . 51 3.3.1 ImpactofNBTIontheEnergyDissipationofAdiabatic LogicCircuits . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.2 ComparisonoftheStressDuetothePermanentNBTIin StaticCMOSandAL . . . . . . . . . . . . . . . . . . . . 58 3.3.3 HowWillPositiveBiasTemperatureInstability(PBTI) ImpactAdiabaticLogic?. . . . . . . . . . . . . . . . . . . 61 4 GenerationofthePower-Clock . . . . . . . . . . . . . . . . . . . . . 65 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 TopologiesofInductor-BasedPower-ClockGenerators . . . . . . 67 4.3 ImpactofPattern-InducedCapacitiveVariationsontheEnergy DissipationoftheSynchronized2N2PLC-oscillator . . . . . . . . 69 4.3.1 ImpactofPattern-InducedVariationsontheDissipationof aDiscrete-CosineTransformation(DCT)System. . . . . . 71 4.4 GenerationoftheSynchronizationSignals . . . . . . . . . . . . . 72 4.4.1 SynchronousVersusAsynchronousGenerationofthe ControlSignalsfortheOscillator . . . . . . . . . . . . . . 73 4.4.2 PartitionsoftheEnergyLossesWithinanAdiabaticSystem 77 5 Power-ClockGating . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.1 IntroductiontoPower-ClockGating . . . . . . . . . . . . . . . . . 83 5.2 TheTheoryofPower-ClockGating . . . . . . . . . . . . . . . . . 84 5.3 GatingTopologiesforPCG . . . . . . . . . . . . . . . . . . . . . 86 5.3.1 Cut-offwithPower-downTransistors . . . . . . . . . . . . 86 5.3.2 Power-downofthePower-ClockOscillator . . . . . . . . . 101 5.4 Power-downModefortheSynchronous2N2PLC-oscillator . . . . 107 6 ArithmeticStructuresinAdiabaticLogic . . . . . . . . . . . . . . . 113 6.1 DesignofArithmeticStructures . . . . . . . . . . . . . . . . . . . 114 6.1.1 FrameworkfortheEstimationofE andA . . . . . 115 diss active 6.1.2 Ripple-CarryAdder(RCA) . . . . . . . . . . . . . . . . . 115 6.1.3 Parallel-PrefixAdders(PPA) . . . . . . . . . . . . . . . . 119 6.2 OverheadReductionbyApplyingComplexGates . . . . . . . . . 128 6.2.1 ImpactofIncreasedInputStackontheEnergyDissipation. 129 6.2.2 Case Study:Energy, LatencyandArea Reductionby ApplyingComplexGatesintheRCAStructure. . . . . . . 130 6.3 Multi-operandAddersandtheCORDICAlgorithm . . . . . . . . 136 6.3.1 NestedRCAStructure . . . . . . . . . . . . . . . . . . . . 136 6.3.2 TheCarry-SaveAdder(CSA)Structure . . . . . . . . . . . 137 6.3.3 ACORDIC-BasedDiscreteCosineTransformation(DCT) 138 7 MeasurementResultsofanAdiabaticFIRFilter . . . . . . . . . . . 145 7.1 StructureoftheAdiabaticFIRFilter . . . . . . . . . . . . . . . . 145 7.2 MeasurementResultsandComparisontoStaticCMOS . . . . . . 149 Contents xi 8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Abbreviations α signalactivityfactor (cid:2) α velocitysaturationfactor(alpha-powerlaw) A,B invertedinputsignalsoflogicgates A crosssectionarea ∗ A activegatearea a ,b inputbiti i i A,B inputsignalsoflogicgate AL adiabaticlogic AST adiabaticsignaltest BK brent-kungPPA BTI biastemperatureinstability (cid:4) C chiralvector h C capacitance C ,C capacitanceoflogicblockF andF F F c carrybiti i c filtercoefficienti i cl bitl offiltercoefficienti i C loadcapacitance L C replacementcapacitance R C switchcapacitance S C tunablecapacitance T C specificoxidecapacitance OX CLA carry-lookaheadadder CMOS complementarymetaloxidesemiconductor CNT carbonnanotube CNTFET carbonnanotubefieldeffecttransistor CORDIC coordinaterotationdigitalcomputer CSA carry-saveadder CSEA carry-selectadder CVSL cascodevoltageswitchlogic (cid:3)C deviationoftheadiabaticloadcapacitance AL xiii

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