Accelerating Test, Validation and Debug of High Speed Serial Interfaces PDF
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Accelerating Test, Validation and Debug of High Speed Serial Interfaces · Yongquan Fan Zeljko Zilic Accelerating Test, Validation and Debug of High Speed Serial Interfaces 123 Dr.YongquanFan Prof.ZeljkoZilic HighPerformanceAnalog DepartmentofElectrical&Computer TexasInstruments Engineering 12500TIBlvd,Dallas,TX75243 McGillUniversity USA UniversityStreet3480 [email protected] H3A2A3Montréal,Québec Canada [email protected] ISBN978-90-481-9397-4 e-ISBN978-90-481-9398-1 DOI10.1007/978-90-481-9398-1 SpringerDordrechtHeidelbergLondonNewYork LibraryofCongressControlNumber:2010938288 (cid:2)c SpringerScience+BusinessMediaB.V.2011 Nopartofthisworkmaybereproduced,storedinaretrievalsystem,ortransmittedinanyformorby anymeans,electronic,mechanical,photocopying,microfilming,recordingorotherwise,withoutwritten permissionfromthePublisher,withtheexceptionofanymaterialsuppliedspecificallyforthepurpose ofbeingenteredandexecutedonacomputersystem,forexclusiveusebythepurchaserofthework. Printedonacid-freepaper SpringerispartofSpringerScience+BusinessMedia(www.springer.com) To Ji Lei Yongquan To Kasia, Maria, Ivan Alexander and Pauline Veronica Zeljko Acknowledgments Authors would like to thank our colleagues and friends at McGill University, Agere Systems/LSI Corporation and Texas Instruments for providing a good environ- ment to conduct this research and finish the book. We especially thank Dr. Yi Cai at LSI for providing longstanding and wise technical advice and co-authoring two papers, Professor Gordon Roberts at McGill for giving research guidelines, Bill Kempler and Sam Yingsheng Tung at Texas Instruments for reviewing the manu- script. A part of the work leading to this book was undertaken while Yongquan Fan was pursuing first his M. Eng. and then Ph. D. degree at McGill University. Our thanks also go to Liming Fang, Anant Verma, Bill Burchanowski, and San- deep Kumar for collaborating on a work that led to co-authoring one paper. We also appreciate the technical support and help from the whole PHY and Storage team at Agere/LSI, especially from Angshu Bhattacharyya, Joe Martone, John Janney, Suri Basharapandiyan, Bernhard Laschinsky, Kevin Richter,P aulH ua,T om Gibson, Kahn Neguen, Bo b Hain and Ken Paist. In addition, we thank the many people who have given valuable advice, feed- back and help at conferences and various other occasions. Special thanks are ex- tended to Mohamed Hafed at DFT Microsystems, Takahiro J. Yamaguchi at Ad- vantest Corporation, Yang Liang at Maxim, Steve Sunter at Logic Vision, Mike Li at Wavecrest (now at Altera), Xu Fang at Teradyne, Joe Venable, Shu Xia and Wai Lee at Texas Instruments, Jwo Cheng and Carlo DiGiovanni from GigOptix, Minh Tran from Teledyne, Mani Soma at University of Washington, Luo He at Concordia University, Warren Gross, Kasia Radecka, Atanu Chattopadhyay, Man-Wah Chiang, Rong Zhang, Milos Prokic and Jean-Samuel Chenard at McGill University Altera Corporation has provided also a great support throughout the years, from their devices and intellectual property, to the encouragement and research funding. Special thanks go to Steve Brown, Fort Blair, Tomasz Czajkowski and David Mendel. At Springer Science+Business Media, Mark de Jongh and Cindy Zitter were always there for us, providing encouragement and cheering the race to the finish line. As with the recent book (Generating Hardware Assertion Checkers, Springer 2008) co-written by Marc Boulé and Zeljko Zilic, the cover page art was drawn by the second author’s children. This time, Maria Zilic took artistic leadership, with vii viii A cknowledgments Ivan and Pauline Zilic doing their share to together depict the effects of the jittery clock in an appealing and a surprisingly lucid way. Last but not least, we would like to thank our whole families for their love and support over the years. Without their support, it would be impossible to undertake all the work and finally write the book. Table of Contents 1 Introduction.......................................................................................................1 1.1 Motivation....................................................................................................1 1.1.1 HSSI Technology Trends.....................................................................2 1.1.2 Qualification Challenges......................................................................5 1.1.3 ATE Perspectives.................................................................................6 1.2 Contributions................................................................................................8 1.3 Overview of the Book..................................................................................9 2 Background.......................................................................................................11 2.1 High-Speed Serial Communication...........................................................11 2.1.1 HSSI Structure....................................................................................14 2.1.2 BER Mechanisms...............................................................................16 2.1.3 Jitter and Noise Impacts to BER........................................................19 2.2 Timing Jitter...............................................................................................21 2.2.1 Jitter Overview...................................................................................21 2.2.2 Jitter and BER....................................................................................23 2.2.3 Jitter Testing.......................................................................................26 2.3 Amplitude Noise........................................................................................28 2.3.1 BER and SNR.....................................................................................28 2.3.2 Simulation and Emulation..................................................................33 2.3.3 AWGN Emulation..............................................................................34 3 Accelerating Receiver Jitter Tolerance Testing on ATE..............................37 3.1 Introduction................................................................................................38 3.1.1 Receiver Structure and Characteristics...............................................38 3.1.2 Jitter Tolerance Testing Overview.....................................................44 3.1.3 Proposed New Method.......................................................................47 3.2 Jitter Test Signal Generation......................................................................51 3.2.1 Choosing Test Signal Parameters.......................................................52 3.2.2 Periodic Jitter Injection......................................................................54 3.2.2.1 Creating Jitter-Free Data Signal.................................................55 3.2.2.2 Creating a Digitized Jitter Signal................................................55 3.2.2.3 Modulating the Data Signal........................................................56 3.2.2.4 Generating Bandwidth Limited Signals......................................57 3.2.2.5 Downsampling to Get AWG Samples........................................59 3.2.3 Fractional Sampling...........................................................................60 3.2.4 Jitter Calibration.................................................................................61 3.2.5 Random Jitter Control........................................................................64 3.3 Receiver Bit Error Monitoring...................................................................65 ix x Ta ble of Contents 3.3.1 ATE-based Error Detection.................................................................66 3.3.2 DFT-based Error Detection.................................................................67 3.4 Jitter Tolerance Extrapolation.....................................................................68 3.4.1 Jitter Tolerance Extrapolation Algorithm...........................................69 3.4.2 Accelerating Jitter Tolerance Characterization...................................72 3.4.3 Accelerating Jitter Tolerance Compliance Testing.............................79 3.4.4 Discussion...........................................................................................81 3.5 Other Applications of the New Method......................................................82 3.5.1 Jitter Transfer Characterization...........................................................82 3.5.2 CDR Characteristics Analysis.............................................................84 4 Transmitter Jitter Extractions on ATE...........................................................87 4.1 Introduction.................................................................................................87 4.1.1 Transmitter Jitter Testing Overview...................................................88 4.1.2 Proposed Solution...............................................................................89 4.2. Test Setup for Data Acquisition................................................................90 4.2.1 Overview of the Test Setup.................................................................90 4.2.2 Principles of Clock Settings................................................................91 4.2.3 Test Setting Parameter Calculations...................................................93 4.3. Jitter Extraction..........................................................................................97 4.3.1 Generating Edge Displacement...........................................................98 4.3.2 Time Domain Approach....................................................................100 4.3.2.1 RJ Extraction.............................................................................102 4.3.2.2 DJ Extraction.............................................................................102 4.3.2.3 TJ Calculation............................................................................103 4.3.3 Frequency Domain Approach...........................................................107 4.3.3.1 RJ Extraction.............................................................................107 4.3.3.2 DJ Extraction.............................................................................108 4.3.4 Hybrid Approach...............................................................................109 4.3.5 Limitations of Each Approach..........................................................111 4.4 Experimental Results................................................................................112 4.4.1 Bench Correlation.............................................................................113 4.4.2 Correlating Two RJ Approaches.......................................................113 4.4.3 Impact of Test Patterns......................................................................115 4.4.4 Impact of the Reference Clock..........................................................116 4.4.5 Extending to 6 Gbps Applications....................................................117 4.5 Summary...................................................................................................118 5 Testing HSSIs with or without ATE Instruments........................................121 5.1 DFT in HSSIs...........................................................................................122 5.1.1 Internal BERT...................................................................................122 5.1.2 Internal Loopback.............................................................................123 5.1.3 Other DFT Techniques......................................................................124 5.1.4 Limitations of DFTs..........................................................................125
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