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A tunable, dual mode field-effect or single electron transistor B. Roche,1 B. Voisin,1 X. Jehl,1,a) R. Wacquez,1,2 M. Sanquer,1 M. Vinet,2 V. Deshpande,2 and B. Previtali2 1)CEA, INAC, SPSMS, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, France 2)CEA, LETI, MINATEC Campus, 17 rue des Martyrs, 38054 GRENOBLE Cedex 9, France (Dated: 19 January 2012) A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has beenfabricatedusingsilicon-on-insulatormetaloxidesemiconductortechnology. Dependingonthebackgate 2 polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field- 1 effecttransistoris obtainedbypinching offa bottomchannelwitha negativefrontgatevoltage. The gradual 0 transition between these two cases is observed. This dual function uses both vertical and horizontal tunable 2 potential gradients in non-overlappedsilicon-on-insulator channel. n a J of the substrate back gate to switch between FET and 8 SET behaviour within the same device, fabricated in a 1 CMOS facility. We have fabricated n-MOSFETs adapted from FD- ] l SOI technology (see Fig.1). The SOI layer is etched to l a pattern the active area above the 150nm thick buried h oxide (BOX). Silicon is then oxidised (5nm) and poly- - s crystallinesiliconisdeposited,resultinginaconventional e gatestack. Aftergateetching,thesourceanddrainmod- m ule is designed. For that purpose silicon nitride spac- . FIG.1. a)Transmissionelectronmicroscope(TEM)imageof ers are formed on both sides of the gate, epitaxy is per- t a adeviceshowingthefrontgate(lengthLg =29nm),channel formed to raise the source and drain, and finally arsenic m (thickness TSi = 12nm) and buried oxide (BOX). The gate is implanted, leading to a typical concentration above - oxide thickness is 5nm. b) TEM image on a larger scale 1020cm−3. Theresultingjunctionprofileissuchthatthe d showing thevariousvoltages applied duringmeasurement,in device is non-overlapped: the undoped region below the n particularthebackgatesubstratevoltage(V )appliedacross bg spacers—acting as a potential barrier for electrons—is o theBOX (150nm thick). c responsible for the SET behaviour described hereafter5. [ The silicon substrate below the BOX is used as a back gate. Thislow-dopedsubstrateusedinindustrialCMOS 1 Owing to its superior control of short channel effect v together with a negligible dopant-induced variability1, processes is not suitable for changing the voltage at low 0 fully-depleted silicon-on-insulator (FD-SOI) is nowadays temperature: tryingtochangethebackgatevoltageleads 6 considered as a consistent solution for future low power to very slow relaxations, of the order of days, making 7 applications2. One of the key challenge for FD-SOI is experiments impossible. Shining light directly over the 3 sample with a red LED thermally anchoredat 4.2K and to design low access resistances. On the other hand sin- . 1 gle electron transistors (SETs) require access resistances an opticalfiber to transmit the light downto lower tem- 0 peraturestages,thesubstratereactsmuchfaster,making of the order of the quantum unit (25.8kΩ) to exhibit 2 Coulomb Blockade Oscillations (CBO)3,4. Hence these substrate polarisation studies possible. The experimen- 1 tal procedure we followed here consists in shining light two devices have so far been designed separately, al- : v though a simple modification of the Source/Drain archi- during only a few seconds after each change of the back i gate voltage value. X tecture enables to get SET operation at low tempera- In this paper we show the data for two devices, how- ture with a metal-oxide-semiconductor field-effect tran- r a sistor(MOS-FET)structure5. SiliconSETs greatlyben- ever many samples have been produced and show the same behaviour. Fig. 1a shows a transmission electron efitfromthematuresilicontechnologies: recentlyscaling micrograph of a device similar to the samples we mea- below the 5nm range allowed room temperature oper- ation6. Coupled SET-FET circuits have been studied sured. for multi-valued logic applications7, realized with silicon The first sample has a channel thickness TSi = 8nm, technologies8 or integrating CMOS devices9. Neverthe- an active width W = 40nm and a gate length Lg = 70nm. Considering the small T andthe relativelylong less a CMOS FD-SOI facility has never been used to re- Si L this sample is designed to have good sub-threshold alize such hybrid circuits, though it is an excellent tool g electrostatic control by the gate. Its electrical charac- to benchmark these concepts. Here we reporton the use teristics at 300K are shown in Fig. 2a in linear and logarithmic scales. It exhibits a sub-threshold slope of 70mV/decade (measured with V = 1mV) which is at d a)[email protected] the state-of-the-art for an oxide thickness of 5nm, close 2 (a) (a) (b) -4 10 -7 10 -5 10-6 18000 x10-6 10-9 Vbg = 0 V S)10 60 G (10-7 4200 10-7 Vg > 0 10-8 -10500 V (mV) 1500 10-9 10--19500 -1000 -500 0 500 g 1000 1500 10-7 V (mV) g S)10-9 (b) 0 (c) 90 G ( mV)-400 (µS)V8700 10-7 V (t-800 GV+1.6 t6500 10--59 Vg < 0 10 -1200 40 0 10 20 30 0 10 20 30 Vbg (V) Vbg (V) 10-7 -9 FIG. 2. a) Sample 1. Drain-source conductance G versus 10 0 20 40 60 frontgatevoltageVg at300KforvariousVbg,rangingfrom0 V - V (mV) Vbg = 39 V (bottom)to39V(top). b)Evolutionofthethresholdvoltage g offset Vt with Vbg. The sub-threshold swing of 70mV/decade is nearly independent of V . c) Drain-source conductance at Vg =Vt+1.6V, i.e. correbcgted for the shift of Vt. Note that it F1IKG.fo3r.V a)=S0a,m1p2,le151,.18,G39Vver(sfurosmVgtop(Vtdo =bot1to0m0µ).V)Thaet increases significantly with V . bg bg curves have been shifted horizontally to show the onset of current (V =400,−30,−210,−300,−890mV resp.). At offset V =0Vand12VregularCBOareobserved. AtV =39V bg bg to the theoreticallimit for thermally activatedtransport only very few aperiodic and broad features are observed at- kBTln(10) (60mV/decade at 300K). tributed to residual single impurity effects. The crossover e does not depend on the absolute value of the conductance G For such an non-overlapped geometry moderate on- but on V only. b) Schematic picture of the device in the current level is expected due to the extra access resis- bg SETregime(top)andintheFETregime(bottom). Thedot- tance to the channel. Fig. 2c shows the variation of the ted areas correspond to high doping region acting as source conductance (in the linear regime) at V = 1.6V above g drain reservoirs at low temperature. An electron gas (green) thethresholdvoltage. Usingapositivebackgatevoltage is either induced by the front gate (SET regime) or by the Vbg, we increase by 20% the normalized value of the on- back gate (FET regime). current,reaching0.4mA/µm(V =39Vandthesource- bg drainbias V =1V, not shown). This is a highvalue for d an etched Si-nanowire. Fig. 2a shows that this gain is obtained without degrading the sub-threshold slope. In- Cg = ∆eVg ≃ 35aF (consistent with the 27aF given by creasing Vbg leads to a decrease of the threshold voltage a planar capacitor model) and the value of conductance (Vt), plotted in Fig. 2b. From the slope dVbg/dVt we foreachoscillationdoesnotchangesignificantlythrough- can obtain the ratio of the effective front gate and back out the V range. This SET regime is well described by g gate capacitances10. We found a ratio of 40 which is the orthodox theory of Coulomb blockade because the not far from a crude estimation with planar capacitors: island contains a large number of electrons at the on- |dVbg/dVt| ≈ TBOX/Tox = 30. The deviation from this set of current. It is useful to note that the flat band model can be explained using a more realistic 3D model condition is reached at V ≃ V ≃ 0 in our devices bg g of capacitances. For practical applications much thinner at T = 0, we can therefor estimate that around one BOX should be used to lower the applied Vbg. hundred electrons are present in the SET on Fig. 3 at At low temperature the non-overlapped geometry of V = 0. The situation changes gradually when increas- bg our FET turns it into a SET without using the back ing V ; the spacing between Coulomb peaks becomes bg gate, as reported before5,11. Here we investigate how larger and irregular, which characterizes a SET with a the device is modified by increasing the substrate volt- much lower density of electrons. The Coulomb island is age at T = 1K. Source-drain conductance is shown on progressivelyfragmented into low electron density flakes Fig. 3 for increasing V . For each V , the V range down to a Coulomb glass regime12. The electron island bg bg g is chosen to see the onset of current through the de- is well defined at V = 0V because the electron gas ex- bg vice. A clear SET regime is found at V = 0V ; the periences sharp gradient of potential at the top of the bg observed CBO are regularly spaced with a period of Si-wire, induced by V . On the contrary these gradients g ∆V = 4.5mV that corresponds to a gate capacitance are smoother near the BOX interface, at a positive back g 3 gate voltages, leading to several electron flakes. There- (a)10-6 fore the sharp transition between high electron density 4.2 K, V = 0 V bg regions and potential barrier—which is necessary for or- -7 10 thodox SET—is progressively lost at large V . Finally, bg for V = 39V, an electron gas is located at the buried bg interfaceandpinchedoffbyanegativefrontgatevoltage, S) 10-8 leadingtoaFETcharacteristic. Theobservedbumpsbe- G ( lowthethresholdareduetoremainingdisorderaffecting 10-9 the smooth parabolic potential of the pinch-off region. The second sample is designed with a reduced Lg of 10-10 30nm. The slightly thicker T is now 12nm and W is Si unchanged. We aim to see the effect of scaling down L 50 100 150 200 250 g both on the SET and the FET. V (mV) g Fig. 4a shows the characteristic of sample 2 at 4.2K (b) and V = 0V. Regular CBO appear due to the non- bg overlapped geometry but the measured period ∆Vg = 10-5 4.2 K, Vbg = +20 V 300 K 21mV±6mV which corresponds to a capacitance Cg = -6 Vbg = 0 V e/∆V ≃8aFislargerbyafactor4ascomparedtosam- 10 g ple 1. This is mainly a consequence of the smaller gate S) length, that is the smaller gate-channel overlap capaci- G ( 10-7 tance. In sample 2 the first few electrons in the island -8 are detected (at Vg >∼ 0). This is due to the larger tun- 10 nel coupling to source and drain at larger T . The low Si -9 10 density limit explains the fluctuations of ∆V through g quantum capacitance effects. -600 -400 -200 0 200 400 By applying V = +20V (red line in Fig. 4b) an ex- V (mV) bg g cellent FET regime is now observed, with both a very steep current rise, and a good on-conductance. We have FIG. 4. a) Sample 2. Coulomb blockade oscillations in the not significantly improved the on-current level as com- source-drain conductance G versus gate voltage at zero back pared to sample 1 because the on-current level is lim- gate voltage. b) In red, the characteristic of the same device ited by the access resistance. The sub-threshold swing at Vbg=+20V. The Coulomb oscillations are replaced by a at T = 4.2K is excellent, reaching 8mV/decade. Com- typical field-effect curve showing an excellent sub-threshold slope of 8mV/decade. For comparison the characteristic at pared to sample 1 less bumps of conductance are ob- 300K and V =0V is also shown. served near the threshold, indicating that the pinch-off bg potential is steeper (smaller gate length) and less sensi- tivetothedisorderedpotential. Thesub-thresholdswing the few electronslimit andimprovesthe FET caracteris- is nevertheless larger than the best theoretical limit at tic at T=4.2K. This work opens up the opportunity to T = 4.2K which is 0.85mV/decade. We attribute the design hybrid circuits with SET and FET devices using observed swing to the thermal activation with a lever a local back gate. Such circuits are well adapted to low arm parameter α = δφ/δV ≃ 0.1 (φ is the potential at g powerapplicationsforwhichtheywillnotsufferfromthe the electron gas location). At V = 0V from the anal- bg relatively high access resistance of the FETs due to the ysis of the CBO we have measured α ≃ 0.3 when the non-overlappedgeometry. electron gas is located near the top interface. The lower Theresearchleadingtotheseresultshasreceivedfund- α value found in the FET regime is consistent with the ing from the European Community’s seventh Frame- fact that the electron gas has been pushed towards the work (FP7 2007/2013) under the Grant Agreement BOX interface. Nr:214989. The samples subject of this work have For comparison the FET characteristic at 300K and beendesignedandmade by the AFSID ProjectPartners V = 0V is shown on the same plot. It exhibits a bg http://www.afsid.eu. sub-threshold swing of 112mV/decade, as a result of its short channel and relatively thicker T . The maximum 1O. Weber, O. Faynot, F. Andrieu, C. Buj-Dufournet, F. Allain, Si transconductance at 4.2K is 30µS (not shown), which P.Scheiblin,J.Foucher,N.Daval,D.Lafond,L.Tosti,etal.,in Tech. Dig. - Int. Electron DevicesMeet. (2008) p.245. makes this FET a good candidate to design an amplifier 2C. Fenouillet-Beranger, P. Perreau, L. Pham-Nguyen, S. De- at cryogenic temperature13. norme, F. Andrieu, L. Tosti, L. Brevard, O.Weber, S.Barnola, Inconclusion,wereportherethefabricationofadevice T. Salvetat, et al., in Tech. Dig. - Int. Electron Devices Meet. acting either asa SET or a FET depending only on sub- (2009)p.667. 3H. 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