3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1

55 Pages·2017·0.88 MB·English

SN54LVT8986,, SN74LVT8986
3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FEATURES
• MembersoftheTexasInstruments (TI)Family • Bypass(BYP –BYP )ForcesPrimaryto
5 0
of JTAGScan-SupportProducts ConfiguredSecondaryPathsWithoutUse of
• ExtendScan AccessFromBoardLevelto LinkingShadowProtocols
HigherLevelofSystemIntegration • Connect(CON –CON )ProvidesIndicationof
2 0
• ThreeIEEE Std1149.1-Compatible Primary-to-SecondaryPathsConnections
Configurable SecondaryScanPathstoOne • SecondaryTAPsCanBeConfiguredat High
PrimaryScanPath ImpedanceVia theOEInputtoAllowan
• MultipleDevicesCanBeCascadedtoLink24 AlternateTestMastertoTakeControlofthe
Secondary ScanPathstoOnePrimaryScan SecondaryTAPs
Path • High-DriveOutputs(–32mAI ,64mAI )
OH OL
• Simple(LinkingShadow)ProtocolIsUsedto SupportBackplaneInterfaceatPrimary
ConnectthePrimaryTestAccessPort (TAP) OutputsandHighFanoutatSecondary
to SecondaryTAPs.ThisSingle ProtocolIs Outputs
UsedtoAddressand Configurethe • WhilePoweredat3.3 V,BothPrimary and
Secondary ScanPath. SecondaryTAPsAreFully5VTolerantfor
• LASP(8986)andASP (8996)CanBe Interfacing5Vand/or3.3 VMastersand
Configured ontheSameBackplaneUsing Targets
SimilarShadowProtocols • PackageOptionsInclude PlasticBGA(GGV)
• LinkingShadowProtocolsCanOccur inAny andLQFP(PM)Packages andCeramic Quad
of TestLogic Reset,RunTest/Idle,PauseDR, Flat(HV)PackagesUsing25-mil
PauseIRTAP StatestoProvide Center-to-CenterSpacing
Board-to-BoardandBuiltInSelfTest
DESCRIPTION/ORDERING INFORMATION
The 'LVT8986 linking addressable scan ports (LASPs) are members of the TI family of IEEE Std 1149.1 (JTAG)
scan-support products. The scan-support product family facilitates testing of fully boundary-scannable devices.
The LASP applies linking shadow protocols through the test access port (TAP) to extend scan access to the
systemlevelanddividescanchainsattheboardlevel.
The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI,
PTMS, PTCK, PTDO, PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1
serial-bus signals. Each secondary TAP consists of signals STDI , STMS , STCK , STDO , and STRST .
x x x x x
Conceptually,theLASPisagatewaydevicethat canbeusedtoconnectaset of primary TAP signals to a set of
secondary TAP signals – for example, to interface backplane TAP signals to a board-level TAP. The LASP
provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP
connections can be configured with the help of linking shadow protocol or protocol bypass (BYP –BYP ) inputs.
5 0
Allpossible configurationsare tabulatedinFunctionTables1,2, and3.
ORDERINGINFORMATION
T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING
A
PBGA–GGV SN74LVT8986GGV LVT8986
–40(cid:176) Cto85(cid:176) C PBGA–ZGV SN74LVT8986ZGV LVT8986
LQFP–PM SN74LVT8986PM LVT8986
–55(cid:176) Cto125(cid:176) C CFP–HV SNJ54LVT8986HV SNJ54LVT8986HV
(1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesign
guidelinesareavailableatwww.ti.com/sc/package.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2002–2007,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not testedunlessotherwisenoted.Onallotherproducts,production
necessarilyincludetestingofallparameters. processingdoesnotnecessarilyincludetestingofallparameters.
SN54LVT8986,, SN74LVT8986
3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
GGVPACKAGE(TOPVIEW)
1 2 3 4 5 6 7 8
A A STRST GND STDO SX GND STMS STDI
0 0 0 O 1 1
B A OE STMS SY V STCK V STDO
1 0 0 CC 1 CC 1
C GND A STCK STDI CON SY GND SX
2 0 0 0 1 1
D A A A A STRST CON V STRST
5 6 4 3 1 1 CC 2
E A A A BYP GND STDI STCK STMS
8 7 9 5 2 2 2
F P P P PTRST PTDO PY SY STDO
0 1 2 2 2
G V BYP BYP PTMS PTDI GND PX SX
CC 0 3 2
H BYP BYP BYP PTCK CTDI CTDO V CON
1 2 4 CC 2
SN74LVT8986...PM PACKAGE
(TOP VIEW)
2
1 T 2 2 2
O 1S K S 2 O 2
CCTD Y1X1ND ON TR CCTC TM TDI NDTD Y2X2ON
V S S S G C S V S S S GS S S C
8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3
4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3
STDI1 49 32 PX
STMS1 50 31 VCC
STCK1 51 30 PY
GND 52 29 GND
STRST1 53 28 CTDO
CON0 54 27 PTDO
SX0 55 26 CTDI
VCC 56 25 PTDI
SY0 57 24 PTMS
STDO0 58 23 PTCK
STDI0 59 22 PTRST
GND 60 21 BYP5
STMS 61 20 BYP
0 4
STCK 62 19 BYP
0 3
STRST 63 18 BYP
0 2
OE 64 17 BYP
1
0 1 2 3 4 5 6
1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1
A 0A 1A 2ND A 3A 4A 5A 6A 7A 8A 9P 0P 1P 2 CC YP 0
G V B
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
SN54LVT8986...HV PACKAGE
(TOP VIEW)
O1 1ST2 K2S2 2 O2 2
CC TD Y1X1 ND ON TR CC C TC TM TDI ND TD Y2X2 ON
V S S S G C S V N S S S G S S S C
0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4
6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4
STDI1 61 43 PX
STMS1 62 42 VCC
STCK1 63 41 PY
GND 64 40 GND
STRST1 65 39 CTDO
CON0 66 38 PTDO
SX0 67 37 CTDI
VCC 68 36 PTDI
NC 1 35 NC
SY 2 34 PTMS
0
STDO 3 33 PTCK
0
STDI 4 32 PTRST
0
GND 5 31 BYP5
STMS0 6 30 BYP4
STCK0 7 29 BYP3
STRST 8 28 BYP
0 2
OE 9 27 BYP
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 1
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2
A 0 A 1A 2 GND A 3A 4 A 5A 6 NC A 7A 8 A 9P 0P 1P 2VCC BYP 0
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered
directly onto the secondary test clock (STCK –STCK ) outputs. Upon power up of the device, the LASP
2 0
assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass
signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting
the primary test reset (PTRST) input or by using the linking shadow protocol. PTRST always is buffered directly
onto the secondary test reset (STRST –STRST ) outputs, ensuring that the LASP and its associated secondary
2 0
TAPscan be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary
test data inputs (STDI –STDI ). Secondary test data outputs (STDO –STDO ) can be configured to receive
2 0 2 0
either the primary test data input (PTDI), STDI –STDI , or the cascade test data input (CTDI). Cascade test data
2 0
output (CTDO) can be configured to receive either of STDI –STDI , or CTDI. CTDI and CTDO facilitate
2 0
cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode
select (STMS –STMS ) outputs can be configured to receive the primary test-mode select (PTMS) input. When
2 0
any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the
secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held
initslaststablestate.
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The address (A –A ) inputs to the LASP are used to identify the LASP. The position (P –P ) inputs to the LASP
9 0 2 0
areusedtoidentifythepositionoftheLASPwithin a cascade chain when multiple LASPs are cascaded. Up to 8
LASPscanbecascadedtolinkamaximumof24secondaryscanpaths to1primaryscanpath.
In a system, primary-to-secondary connection is based on linking shadow protocols that are received and
acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states,
other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential
nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being
configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and
position bits received serially at PTDI match those at the parallel address (A –A ) inputs and position (P –P )
9 0 2 0
inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking
shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and
assumes the connected (ON) status. If the received address or position does not match that at the address
(A –A ) inputs or position (P –P ) inputs, the LASP immediately assumes the disconnected (OFF) status,
9 0 2 0
withoutacknowledgment.
The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs
respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to
disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures
that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the
secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA)
causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the
LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration of
the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple LASPs.
This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle state,
and scanning of common test data into multiple like scan chains. The MULTICAST status may also be useful for
concurrent in-system programming (ISP) of common modules. The TSA is valid only when received in the
Pause-DRorPause-IRTAP states.RefertoTable9for differentaddressmapping.
Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP )
5
input. The remaining bypass (BYP –BYP ) inputs are used for configuring the secondary TAPs as shown in
4 0
Table 1 and Table 2. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up
reset. This bypassing feature is especially useful in the board-test environment because it allows board-level
automatedtestequipment(ATE)totreattheLASPasasimple transceiver. When BYP is high, the LASP is free
5
to respond to linking shadow protocols. Otherwise, when BYP is low, linking shadow protocols are ignored.
5
Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this
status is indicated by a low level at the connect (CON –CON ) outputs. Likewise, when the secondary TAP is
2 0
disconnected from the primary TAP, the corresponding CON output is high. Each secondary TAP has a
pass-through input and output consisting of SX –SX and SY –SY , respectively. Similarly, the primary TAP also
2 0 2 0
hasapass-throughinputandoutput consisting of PX and PY, respectively. Pass-through input PX drives the SY
outputsofthesecondaryTAPsthatareconnectedtothe primaryTAP. Disconnected secondary TAPs have their
SY outputs at high impedance. Pass-through inputs SY –SY of the connected secondary TAPs are logically
2 0
ANDedanddrivethePYoutput.RefertoTable4-7for pass-throughinput/output operation.
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FUNCTIONALBLOCKDIAGRAM
VCC VCC
CTDI STDI2
CTDO STCK2
STRST2
PTCK STMS2
VCC
STDO2
PTRST
VCC
CON2
PTMS SY2
VCC VCC
PTDI SX2
VCC
STDI1
PTDO
STCK1
Secondary STRST1
TAP Network
STMS1
STDO1
CON1
Linking Shadow SY1
VCC Protocol VCC
Transmit
A0–A9 SX1
VCC VCC
P0–P2 STDI0
VCC
BYP0–BYP5 Connect STCK0
Control STRST0
STMS0
VCC STDO0
PX CON0
PY SY0
Linking Shadow VCC
Protocol
Receive SX0
OE
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FUNCTIONTABLE1
(Primary-to-SecondaryConnectStatus)
INPUTS PRIMARY- OUTPUTS
LINKINGSHADOW TO-SECONDARY
BYP BYP BYP BYP BYP BYP PTRST PROTOCOLRESULT CONNECT CON CON CON
5 4 3 2 1 0 2 1 0
STATUS
L X X H H H L – BYP/TRST H H H
L X X H H L L – BYP/TRST H H L
L X X H L H L – BYP/TRST H L H
L X X H L L L – BYP/TRST H L L
L X X L H H L – BYP/TRST L H H
L X X L H L L – BYP/TRST L H L
L X X L L H L – BYP/TRST L L H
L X X L L L L – BYP/TRST L L L
L X X H H H H – BYP H H H
L X X H H L H – BYP H H L
L X X H L H H – BYP H L H
L X X H L L H – BYP H L L
L X X L H H H – BYP L H H
L X X L H L H – BYP L H L
L X X L L H H – BYP L L H
L X X L L L H – BYP L L L
H X X X X X L – TRST H H H
H X X X X X H RESET RESET H H H
H X X X X X H MATCH ON SeeFunctionTable3
H X X X X X H NOMATCH OFF H H H
H X X X X X H HARDERROR OFF H H H
H X X X X X H DISCONNECT OFF H H H
TEST
H X X X X X H MULTICAST SeeNote (1)
SYNCHRONIZATION
(1) Theresultofreceiptofthetestsynchronizationaddress(TSA)onasecondaryTAP,whoseTAPstateisPause-DRorPause-IR,isON
andthecorrespondingCONoutputissetlow.TheresultofreceiptoftheTSAonasecondaryTAPwhoseTAPstateis
Test-Logic-ResetorRun-Test-Idleisdisconnect,andthecorrespondingCONoutputissethigh.
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FUNCTIONTABLE2
(SecondaryTAPConfigurationUsingBypassInputs)
INPUTS OUTPUTS
LINKINGSHADOW
BYP5–0 PTRST PROTOCOLRESULT ST2R–0ST S2T–C0K STMS2 STMS1 STMS0 STDO2 STDO1 STDO0 PTDO CTDO
LLLHHH L L PTCK H(1) H(1) H(1) Z Z Z Z CTDI
LLLHHL L L PTCK H(1) H(1) H(1) Z Z PTDI STDI0 STDI0
LLLHLH L L PTCK H(1) H(1) H(1) Z PTDI Z STDI1 STDI1
LLLHLL L L PTCK H(1) H(1) H(1) Z STDI0 PTDI STDI1 STDI1
LLLLHH L L PTCK H(1) H(1) H(1) PTDI Z Z STDI2 STDI2
LLLLHL L L PTCK H(1) H(1) H(1) STDI0 Z PTDI STDI2 STDI2
LLLLLH L L PTCK H(1) H(1) H(1) STDI1 PTDI Z STDI2 STDI2
LLLLLL L L PTCK H(1) H(1) H(1) STDI1 STDI0 PTDI STDI2 STDI2
xxx
LLHHHH L L PTCK H(1) H(1) H(1) Z Z Z Z CTDI
LLHHHL L L PTCK H(1) H(1) H(1) Z Z PTDI Z STDI0
LLHHLH L L PTCK H(1) H(1) H(1) Z PTDI Z Z STDI1
LLHHLL L L PTCK H(1) H(1) H(1) Z STDI0 PTDI Z STDI1
LLHLHH L L PTCK H(1) H(1) H(1) PTDI Z Z Z STDI2
LLHLHL L L PTCK H(1) H(1) H(1) STDI0 Z PTDI Z STDI2
LLHLLH L L PTCK H(1) H(1) H(1) STDI1 PTDI Z Z STDI2
LLHLLL L L PTCK H(1) H(1) H(1) STDI1 STDI0 PTDI Z STDI2
xxx
LHLHHH L L PTCK H(1) H(1) H(1) Z Z Z Z CTDI
LHLHHL L L PTCK H(1) H(1) H(1) Z Z CTDI STDI0 STDI0
LHLHLH L L PTCK H(1) H(1) H(1) Z CTDI Z STDI1 STDI1
LHLHLL L L PTCK H(1) H(1) H(1) Z STDI0 CTDI STDI1 STDI1
LHLLHH L L PTCK H(1) H(1) H(1) CTDI Z Z STDI2 STDI2
LHLLHL L L PTCK H(1) H(1) H(1) STDI0 Z CTDI STDI2 STDI2
LHLLLH L L PTCK H(1) H(1) H(1) STDI1 CTDI Z STDI2 STDI2
LHLLLL L L PTCK H(1) H(1) H(1) STDI1 STDI0 CTDI STDI2 STDI2
xxx
LHHHHH L L PTCK H(1) H(1) H(1) Z Z Z Z CTDI
LHHHHL L L PTCK H(1) H(1) H(1) Z Z CTDI Z STDI0
LHHHLH L L PTCK H(1) H(1) H(1) Z CTDI Z Z STDI1
LHHHLL L L PTCK H(1) H(1) H(1) Z STDI0 CTDI Z STDI1
LHHLHH L L PTCK H(1) H(1) H(1) CTDI Z Z Z STDI2
LHHLHL L L PTCK H(1) H(1) H(1) STDI0 Z CTDI Z STDI2
LHHLLH L L PTCK H(1) H(1) H(1) STDI1 CTDI Z Z STDI2
LHHLLL L L PTCK H(1) H(1) H(1) STDI1 STDI0 CTDI Z STDI2
xxx
LLLHHH H H PTCK STMS2(2) STMS1(2) STMS0(2) Z Z Z Z CTDI
LLLHHL H H PTCK STMS2(2) STMS1(2) PTMS Z Z PTDI STDI0 STDI0
LLLHLH H H PTCK STMS2(2) PTMS STMS0(2) Z PTDI Z STDI1 STDI1
LLLHLL H H PTCK STMS2(2) PTMS PTMS Z STDI0 PTDI STDI1 STDI1
(1) InnormaloperationofIEEEStd1149.1-compliantarchitectures,itisrecommendedthatTMSbehighpriortoreleaseofSTRST.The
BYP/STRSTconnectstatusensuresthatthisconditionismetatSTMS,regardlessoftheappliedPTMS.Also,itisrecommendedthat
STMSbekepthighforaminimumdurationoffivePTCKcyclesfollowingassertionofPTRST,eitherbymaintainingPTRSTloworby
settingPTMShigh.ThisensuresthatdeviceswithandwithoutSTRSTinputsaremovedtotheirTest-Logic-ResetTAPstates.Itis
expectedthat,innormalapplication,thisconditionoccursonlywhenBYP isfixedatthelowstate.Insuchacase,uponreleaseof
5
PTRST,theLASPimmediatelyresumestheBYPconnectstatus.
(2) STMSlevelbeforesteady-stateconditionswereestablished
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3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FUNCTIONTABLE2
(SecondaryTAP ConfigurationUsingBypassInputs)(Continued)
INPUTS OUTPUTS
LINKINGSHADOW
BYP5–0 PTRST PROTOCOLRESULT ST2R0ST S2T–C0K STMS2 STMS1 STMS0 STDO2 STDO1 STDO0 PTDO CTDO
LLLLHH H H(1) PTCK PTMS STMS1(2) STMS0(2) PTDI Z Z STDI2 STDI2
LLLLHL H H PTCK PTMS STMS1(2) PTMS STDI0 Z PTDI STDI2 STDI2
LLLLLH H H PTCK PTMS PTMS STMS0(2) STDI1 PTDI Z STDI2 STDI2
LLLLLL H H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI STDI2 STDI2
xxx
LLHHHH H H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
LLHHHL H H PTCK STMS2(3) STMS1(3) PTMS Z Z PTDI Z STDI0
LLHHLH H H PTCK STMS2(3) PTMS STMS0(3) Z PTDI Z Z STDI1
LLHHLL H H PTCK STMS2(3) PTMS PTMS Z STDI0 PTDI Z STDI1
LLHLHH H H PTCK PTMS STMS1(3) STMS0(3) PTDI Z Z Z STDI2
LLHLHL H H PTCK PTMS STMS1(3) PTMS STDI0 Z PTDI Z STDI2
LLHLLH H H PTCK PTMS PTMS STMS0(3) STDI1 PTDI Z Z STDI2
LLHLLL H H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI Z STDI2
xxx
LHLHHH H H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
LHLHHL H H PTCK STMS2(3) STMS1(3) PTMS Z Z CTDI STDI0 STDI0
LHLHLH H H PTCK STMS2(3) PTMS STMS0(3) Z CTDI Z STDI1 STDI1
LHLHLL H H PTCK STMS2(3) PTMS PTMS Z STDI0 CTDI STDI1 STDI1
LHLLHH H H PTCK PTMS STMS1(3) STMS0(3) CTDI Z Z STDI2 STDI2
LHLLHL H H PTCK PTMS STMS1(3) PTMS STDI0 Z CTDI STDI2 STDI2
LHLLLH H H PTCK PTMS PTMS STMS0(3) STDI1 CTDI Z STDI2 STDI2
LHLLLL H H PTCK PTMS PTMS PTMS STDI1 STDI0 CTDI STDI2 STDI2
xxx
LHHHHH H H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
LHHHHL H H PTCK STMS2(3) STMS1(3) PTMS Z Z CTDI Z STDI0
LHHHLH H H PTCK STMS2(3) PTMS STMS0(3) Z CTDI Z Z STDI1
LHHHLL H H PTCK STMS2(3) PTMS PTMS Z STDI0 CTDI Z STDI1
LHHLHH H H PTCK PTMS STMS1(3) STMS0(3) CTDI Z Z Z STDI2
LHHLHL H H PTCK PTMS STMS1(3) PTMS STDI0 Z CTDI Z STDI2
LHHLLH H H PTCK PTMS PTMS STMS0(3) STDI1 CTDI Z Z STDI2
LHHLLL H H PTCK PTMS PTMS PTMS STDI1 STDI0 CTDI Z STDI2
xxx
HXXXXX L L PTCK H H H Z Z Z Z H
HXXXXX H RESET H PTCK H H H Z Z Z Z CTDI
HXXXXX H MATCH H PTCK SeeFunctionTable3
HXXXXX H NOMATCH H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
HXXXXX H HARDERROR(4) H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
HXXXXX H DISCONNECT H PTCK STMS2(3) STMS1(3) STMS0(3) Z Z Z Z CTDI
TEST
HXXXXX H H PTCK PTMS(5) PTMS(5) PTMS(5) PTDI(5) PTDI(5) PTDI(5) Z CTDI
SYNCHRONIZATION
(1) InnormaloperationofIEEEStd1149.1-compliantarchitectures,itisrecommendedthatTMSbehighpriortoreleaseofTRST.The
BYP/TRSTconnectstatusensuresthatthisconditionismetatSTMS,regardlessoftheappliedPTMS.Also,itisrecommendedthat
STMSbekepthighforaminimumdurationoffivePTCKcyclesfollowingassertionofPTRST,eitherbymaintainingPTRSTloworby
settingPTMShigh.ThisensuresthatdeviceswithandwithoutTRSTinputsaremovedtotheirTest-Logic-ResetTAPstates.Itis
expectedthat,innormalapplication,thisconditionoccursonlywhenBYP5isfixedatthelowstate.Insuchacase,uponreleaseof
PTRST,theLASPimmediatelyresumestheBYPconnectstatus.
(2) STMSlevelbeforesteady-stateconditionswereestablished
(3) STMSlevelbeforesteady-stateconditionswereestablished
(4) Thelinkingshadowprotocoliswelldefined.Somevariationsintheprotocolaretolerated(seeprotocolerrors).Thosethatarenot
toleratedproducetheresultHARDERRORandcausedisconnect,asindicated.
(5) PTDIandPTMSareconnectedtoSTDOandSTMS,respectively,onlyonthosesecondaryTAPswhoseTAPstateisPause-DRor
Pause-IRwhilePTDOishighimpedance.TheresultoflinkingshadowprotocolonasecondaryTAPwhosestateisTest-Logic-Resetor
Run-Test-IdleisDISCONNECT.
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SN54LVT8986,, SN74LVT8986
3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
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SN54LVT8986,, SN74LVT8986
3.3-VLINKINGADDRESSABLESCANPORTS
MULTIDROP-ADDRESSABLEIEEESTD1149.1(JTAG)TAPTRANSCEIVERS
www.ti.com
SCBS759E–OCTOBER2002–REVISEDMAY2007
FUNCTIONTABLE3
(SecondaryTAPConfigurationUsingLinkingShadowProtocol)
CONFI
G STRST STCK
POSITION BITS 2–0 2–0 STMS2 STMS1 STMS0 STDO2 STDO1 STDO0 PTDO CTDO CON2 CON1 CON0
2–0
HHH H PTCK STMS2(1) STMS1(1) STMS0(1) Z Z Z Z CTDI H H H
HHL H PTCK STMS2(1) STMS1(1) PTMS Z Z PTDI STDI0 STDI0 H H L
HLH H PTCK STMS2(1) PTMS STMS0(1) Z PTDI Z STDI1 STDI1 H L H
Single HLL H PTCK STMS2(1) PTMS PTMS Z STDI0 PTDI STDI1 STDI1 H L L
device LHH H PTCK PTMS STMS1(1) STMS0(1) PTDI Z Z STDI2 STDI2 L H H
LHL H PTCK PTMS STMS1(1) PTMS STDI0 Z PTDI STDI2 STDI2 L H L
LLH H PTCK PTMS PTMS STMS0(1) STDI1 PTDI Z STDI2 STDI2 L L H
LLL H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI STDI2 STDI2 L L L
HHH H PTCK STMS2(1) STMS1(1) STMS0(1) Z Z Z Z CTDI H H H
HHL H PTCK STMS2(1) STMS1(1) PTMS Z Z PTDI Z STDI0 H H L
HLH H PTCK STMS2(1) PTMS STMS0(1) Z PTDI Z Z STDI1 H L H
Firstdevicein HLL H PTCK STMS2(1) PTMS PTMS Z STDI0 PTDI Z STDI1 H L L
cascade
chain LHH H PTCK PTMS STMS1(1) STMS0(1) PTDI Z Z Z STDI2 L H H
LHL H PTCK PTMS STMS1(1) PTMS STDI0 Z PTDI Z STDI2 L H L
LLH H PTCK PTMS PTMS STMS0(1) STDI1 PTDI Z Z STDI2 L L H
LLL H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI Z STDI2 L L L
HHH H PTCK STMS2(1) STMS1(1) STMS0(1) Z Z Z Z CTDI H H H
HHL H PTCK STMS2(1) STMS1(1) PTMS Z Z CTDI Z STDI0 H H L
Norfirstand HLH H PTCK STMS2(1) PTMS STMS0(1) Z CTDI Z Z STDI1 H L H
notlast HLL H PTCK STMS2(1) PTMS PTMS Z STDI0 CTDI Z STDI1 H L L
devicein
cascade LHH H PTCK PTMS STMS1(1) STMS0(1) CTDI Z Z Z STDI2 L H H
chain LHL H PTCK PTMS STMS1(1) PTMS STDI0 Z PTDI Z STDI2 L H L
LLH H PTCK PTMS PTMS STMS0(1) STDI1 CTDI Z Z STDI2 L L H
LLL H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI Z STDI2 L L L
HHH H PTCK STMS2(1) STMS1(1) STMS0(1) Z Z Z Z CTDI H H H
HHL H PTCK STMS2(1) STMS1(1) PTMS Z Z CTDI STDI0 STDI0 H H L
HLH H PTCK STMS2(1) PTMS STMS0(1) Z CTDI Z STDI1 STDI1 H L H
Lastdevicein HLL H PTCK STMS2(1) PTMS PTMS Z STDI0 CTDI STDI1 STDI1 H L L
cascade
chain LHH H PTCK PTMS STMS1(1) STMS0(1) CTDI Z Z STDI2 STDI2 L H H
LHL H PTCK PTMS STMS1(1) PTMS STDI0 Z PTDI STDI2 STDI2 L H L
LLH H PTCK PTMS PTMS STMS0(1) STDI1 CTDI Z STDI2 STDI2 L L H
LLL H PTCK PTMS PTMS PTMS STDI1 STDI0 PTDI STDI2 STDI2 L L L
(1) STMSlevelbeforesteady-stateconditionswereestablished
In order to provide the ability to cascade multiple LASPs, pad bits are used to reduce propagation delays that
reduce the allowable test clock speed. These pad bits are located along the internal scan path of the LASP and,
therefore, must be accommodated in the boundary-scan test program. The number of these bits ranges from
onetofour.Thenumberandlocationcompletelydepends on the configuration of the LASP. In Function Table 4,
eachLASPrelative positionandconfiguration scanpath usesa(1)to indicateapadbit inthepath.
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