1.2-V 12/10/8-Bit 200-KSPS/100-KSPS MICRO-POWER MINIATURE ADC s/Serial Interface

28 Pages·2016·1.07 MB·English

(cid:2)(cid:17)(cid:14)(cid:14)(cid:20)(cid:2)(cid:14)(cid:13)(cid:18)(cid:12)(cid:0)(cid:4)(cid:14)(cid:13)(cid:8)(cid:17)(cid:7)(cid:16)(cid:15) ADS7866
(cid:10)(cid:14)(cid:13)(cid:11)(cid:0)(cid:5)(cid:9)(cid:19)(cid:6)(cid:15)(cid:0) (cid:3)(cid:12)(cid:15)(cid:16)(cid:14)(cid:17)(cid:11)(cid:9)(cid:12)(cid:16)(cid:15)
ADS7867
ADS7868
SLAS465–JUNE2005
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
FEATURES The sampling, conversion, and activation of digital
• Single1.2-Vto3.6-V SupplyOperation output SDO are initiated on the falling edge of CS.
The serial clock SCLK is used for controlling the
• HighThroughput
conversion rate and shifting data out of the converter.
– 200/240/280KSPSfor 12/10/8-BitV ‡ 1.6V Furthermore, SCLK provides a mechanism to allow
DD
– 100/120/140KSPSfor 12/10/8-BitV ‡ 1.2V digital host processors to synchronize with the con-
DD verter. These converters interface with
• – 1.5LSBINL,12-BitNMC(ADS7866)
micro-processors or DSPs through a high-speed SPI
• 71dBSNR,–83dBTHDatf =30kHz compatible serial interface. There are no pipeline
IN
(ADS7866) delaysassociatedwith thedevice.
• SynchronizedConversion withSCLK The minimum conversion time is determined by the
• SPICompatibleSerialInterface frequency of the serial clock input, SCLK, while the
• NoPipelineDelays maximum frequency of SCLK is determined by the
minimum sampling time required to charge the input
• LowPower capacitance to 12/10/8-bit accuracy for the
– 1.39mWTyp at200KSPS, V =3.6V ADS7866/67/68, respectively. The maximum
DD
throughput is determined by how often a conversion
– 0.39mWTyp at200KSPS, V =1.6V
DD is initiated when the minimum sampling time is met
– 0.22mWTyp at100KSPS, V =1.2V
DD and the maximum SCLK frequency is used. Each
• AutoPower-Down:8nA Typ,300nA Max device automatically powers down after each conver-
• 0VtoV Unipolar InputRange sion, which allows each device to save power when
DD
the throughput is reduced while using the maximum
• 6-PinSOT-23Package
SCLKfrequency.
APPLICATIONS The converter reference is taken internally from the
• BatteryPoweredSystems supply. Hence, the analog input range for these
devicesis0VtoV .
• IsolatedDataAcquisition DD
• MedicalInstruments These devices are available in a 6-pin SOT-23
package and are characterized over the industrial
• PortableCommunication –40(cid:176) Cto 85(cid:176) Ctemperaturerange.
• PortableDataAcquisitionSystems
• AutomaticTestEquipment
REF/VDD
DESCRIPTION
12/10/8 BIT ADC
The ADS7866/67/68 are low power, miniature, Comparator
12/10/8-bit A/D converters each with a unipolar, VIN +
_S/H CDAC
single-endedinput.Thesedevicescanoperatefroma
Conversion CS
single 1.6 V to 3.6 V supply with a 200-KSPS and SCLK
SAR Control
throughput for ADS7866. In addition, these devices Logic SDO
can maintain at least a 100-KSPS throughput with a
supplyaslowas 1.2V.
GND
Micro-PowerMiniature SARConverterFamily
RESOLUTION/SPEED <200KSPS 1MSPS–1.25MSPS
12-Bit ADS7866(1.2V to3.6V ) ADS7886(2.35V to5.25V )
DD DD DD DD
10-Bit ADS7867(1.2V to3.6V ) ADS7887(2.35V to5.25V )
DD DD DD DD
8-Bit ADS7868(1.2V to3.6V ) ADS7888(2.35V to5.25V )
DD DD DD DD
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2005,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placedin conductivefoamduringstorageorhandlingtoprevent electrostaticdamageto theMOSgates.
ORDERINGINFORMATION(1)
MAXIMUM MAXIMUM NOMISSING
PACKAGE SPECIFIED TRANSPORT
INTEGRAL DIFFERENTIAL CODES PACKAGE PACKAGE ORDERING
MODEL MARKING TEMPERATURE MEDIA,
LINEARITY LINEARITY RESOLULTION TYPE DESIGNATOR NUMBER
(SYMBOL) RANGE QUANTITY
(LSB) (LSB) (BIT)
ADS7866I – 1.5 –1/+1.5 12 SOT23-6 A66Y DBV –40(cid:176)Cto85(cid:176)C ADS7866IDBVT Smalltapeandreel,250
ADS7866I – 1.5 –1/+1.5 12 SOT23-6 A66Y DBV –40(cid:176)Cto85(cid:176)C ADS7866IDBVR Tapeandreel,3000
ADS7867I – 0.5 – 0.5 10 SOT23-6 A67Y DBV –40(cid:176)Cto85(cid:176)C ADS7867IDBVT Smalltapeandreel,250
ADS7867I – 0.5 – 0.5 10 SOT23-6 A67Y DBV –40(cid:176)Cto85(cid:176)C ADS7867IDBVR Tapeandreel,3000
ADS7868I – 0.5 – 0.5 8 SOT23-6 A68Y DBV –40(cid:176)Cto85(cid:176)C ADS7868IDBVT Smalltapeandreel,250
ADS7868I – 0.5 – 0.5 8 SOT23-6 A68Y DBV –40(cid:176)Cto85(cid:176)C ADS7868IDBVR Tapeandreel,3000
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
ABSOLUTE MAXIMUM RATINGS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
RATING
V toGND –0.3Vto4.0V
DD
AnaloginputvoltagetoGND –0.3VtoV +0.3V
DD
DigitalinputvoltagetoGND –0.3Vto4.0V
DigitaloutputvoltagetoGND –0.3VtoV +0.3V
DD
T Operatingfree-airtemperaturerange –40(cid:176) Cto85(cid:176) C
A
T Storagetemperaturerange –65(cid:176) Cto150(cid:176) C
STORAGE
T Junctiontemperature 150(cid:176) C
J
q Thermalimpedance 110.9(cid:176) C/W
JA
SOT-23Package
q Thermalimpedance 22.31(cid:176) C/W
JC
Leadtemperature, Vaporphase(10–40sec) 250(cid:176) C
soldering Infrared(10–30sec) 260(cid:176) C
ESD 3kV
2
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7866
At–40(cid:176) Cto85(cid:176) C,f =200KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =100KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
SYSTEMPERFORMANCE
Resolution 12 Bits
Nomissingcodes 12 Bits
Integrallinearity –1.5 1.5 LSB(1)
Differentiallinearity –1 1.5 LSB
Offseterror(2) 1.2V£ VDD<1.6V –2 2 LSB
1.6V£ VDD£ 3.6V –3 3
Gainerror(3) 1.2V£ VDD<1.6V –2 2 LSB
1.6V£ VDD£ 3.6V –2 2
Totalunadjustederror(4) 1.2V£ VDD<1.6V –2.5 2.5 LSB
1.6V£ VDD£ 3.6V –3.5 3.5
SAMPLINGDYNAMICS(SeeTimingCharacteristicsSection)
tCONVERT Conversiontime fSCLK=3.4MHz,13SCLKcycles 3.82 µs
tSAMPLE Acquisitiontime fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 0.64 µs
fSAMPLE Throughputrate fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 200 KSPS
Aperturedelay 10 ns
Aperturejitter 40 ps
DYNAMICCHARACTERISTICS
Signal-to-noise fIN=30kHz,1.2V£ VDD<1.6V 68
SINAD dB
anddistortion fIN=30kHz,1.6V£ VDD£ 3.6V 69 70
fIN=30kHz,1.2V£ VDD<1.6V 70
SNR Signal-to-noiseratio dB
fIN=30kHz,1.6V£ VDD£ 3.6V 70 71
THD Totalharmonicdistortion(5) fIN=30kHz,1.2V£ VDD<1.6V –70 dB
fIN=30kHz,1.6V£ VDD£ 3.6V –83
Spuriousfreedynamic fIN=30kHz,1.2V£ VDD<1.6V 75
SFDR dB
range fIN=30kHz,1.6V£ VDD£ 3.6V 85
At0.1dB,1.2V£ VDD<1.6V 2
Full-powerbandwidth(6) At0.1dB,1.6V£ VDD£ 3.6V 4 MHz
At3dB,1.2V£ VDD<1.6V 3
At3dB,1.6V£ VDD£ 3.6V 8
ANALOGINPUT
Full-scaleinputspan(7) VIN–GND 0 VDD V
CS Inputcapacitance 12 pF
Inputleakagecurrent –1 1 µA
DIGITALINPUT
Logicfamily,CMOS
1.2V£ VDD<1.6V 0.7· VDD 3.6
1.6V£ VDD<1.8V 0.7· VDD 3.6
VIH Inputlogichighlevel 1.8V£ VDD<2.5V 0.7· VDD 3.6 V
2.5V£ VDD£ 3.6V 2 3.6
(1) LSB=LeastSignificantBIt
(2) Thedifferenceinthefirstcodetransition000...000to000...001fromtheidealvalueofGND+1LSB.
(3) Thedifferenceinthelastcodetransition011...111to111...111fromtheidealvalueofV -1LSBwiththeoffseterrorremoved.
DD
(4) Theabsolutedifferencefromtheidealtransferfunctionoftheconverter.ThisspecificationissimilartoINLerrorexcepttheeffectsof
offseterrorandgainerrorareincluded.
(5) The2ndthrough10thharmonicsareusedtodetermineTHD.
(6) Inputfrequencywheretheamplitudeofthedigitizedsignalhasdecreasedby0.1dBor3dB.
(7) Idealinputspanwhichdoesnotincludegainoroffseterrors.
3
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7866 (continued)
At–40(cid:176) Cto85(cid:176) C,f =200KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =100KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
1.2V£ VDD<1.6V –0.2 0.2· VDD
1.6V£ VDD<1.8V –0.2 0.2· VDD
VIL Inputlogiclowlevel 1.8V£ VDD<2.5V –0.2 0.3· VDD V
2.5V£ VDD£ 3.6V –0.2 0.8
ISCLK SCLKpinleakagecurrent Digitalinput=0VorVDD –1 0.02 1 µA
ICS CSpinleakagecurrent – 1 µA
CIN Digitalinputpincapacitance 10 pF
DIGITALOUTPUT
VOH Outputlogichighlevel ISOURCE=200µA VDD–0.2 VDD V
VOL Outputlogiclowlevel ISINK=200µA 0 0.2 V
ISDO SDOpinleakagecurrent Floatingoutput –1 1 µA
Digitaloutputpin
COUT capacitance Floatingoutput 10 pF
Dataformat,straightbinary
POWERSUPPLYREQUIREMENTS
VDD Supplyvoltage 1.2 3.6 V
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=3.6V 385 500
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=3.6V 193
µA
fSAMPLE=50KSPS,fSCLK=3.4MHz,VDD=3.6V 97
fSAMPLE=20KSPS,fSCLK=3.4MHz,VDD=3.6V 39
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=3V 340
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=3V 170
µA
fSAMPLE=50KSPS,fSCLK=3.4MHz,VDD=3V 85
fSAMPLE=20KSPS,fSCLK=3.4MHz,VDD=3V 35
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=2.5V 305
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=2.5V 153
µA
fSAMPLE=50KSPS,fSCLK=3.4MHz,VDD=2.5V 77
Supplycurrent, Digitalinputs=0V
IDD normaloperation orVDD fSAMPLE=20KSPS,fSCLK=3.4MHz,VDD=2.5V 31
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=1.8V 256
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=1.8V 128
µA
fSAMPLE=50KSPS,fSCLK=3.4MHz,VDD=1.8V 65
fSAMPLE=20KSPS,fSCLK=3.4MHz,VDD=1.8V 26
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=1.6V 241 330
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=1.6V 121
µA
fSAMPLE=50KSPS,fSCLK=3.4MHz,VDD=1.6V 61
fSAMPLE=20KSPS,fSCLK=3.4MHz,VDD=1.6V 25
fSAMPLE=100KSPS,fSCLK=1.7MHz,VDD=1.2V 186 250
fSAMPLE=50KSPS,fSCLK=1.7MHz,VDD=1.2V 93 µA
fSAMPLE=20KSPS,fSCLK=1.7MHz,VDD=1.2V 37
IDD Power-downmode SCLKonoroff 0.008 0.3 µA
POWERDISSIPATION
fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=3.6V 1.39 1.80
Normaloperation fSAMPLE=200KSPS,fSCLK=3.4MHz,VDD=1.6V 0.39 0.53 mW
fSAMPLE=100KSPS,fSCLK=1.7MHz,VDD=1.2V 0.22 0.3
Power-downmode SCLKonoroff,VDD=3.6V 1.08 µW
TEMPERATURERANGE
Specifiedperformance –40 85 (cid:176)C
4
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7867
At–40(cid:176) Cto85(cid:176) C,f =240KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =120KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
SYSTEMPERFORMANCE
Resolution 10 Bits
Nomissingcodes 10 Bits
Integrallinearity –0.5 0.5 LSB(1)
Differentiallinearity –0.5 0.5 LSB
Offseterror(2) 1.2V£ VDD<1.6V –0.75 0.75 LSB
1.6V£ VDD£ 3.6V –1 1
Gainerror(3) 1.2V£ VDD<1.6V –0.5 0.5 LSB
1.6V£ VDD£ 3.6V –0.5 0.5
Totalunadjustederror(4) 1.2V£ VDD<1.6V –2 2 LSB
1.6V£ VDD£ 3.6V –2 2
SAMPLINGDYNAMICS(SeeTimingCharacteristicsSection)
tCONVERT Conversiontime fSCLK=3.4MHz,11SCLKcycles 3.235 µs
tSAMPLE Acquisitiontime fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 0.64 µs
fSAMPLE Throughputrate fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 240 KSPS
Aperturedelay 10 ns
Aperturejitter 40 ps
DYNAMICCHARACTERISTICS
Signal-to-noise fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 61
SINAD dB
anddistortion fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 61 61.7
fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 61.5
SNR Signal-to-noiseratio dB
fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 61.8
THD Totalharmonicdistortion(5) fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V -68 dB
fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V -78 -72
fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 73
SFDR Spuriousfreedynamicrange dB
fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 74 80
At0.1dB,1.2V£ VDD<1.6V 2
Full-powerbandwidth(6) At0.1dB,1.6V£ VDD£ 3.6V 4 MHz
At3dB,1.2V£ VDD<1.6V 3
At3dB,1.6V£ VDD£ 3.6V 8
ANALOGINPUT
Full-scaleinputspan(7) VIN–GND 0 VDD V
CS Inputcapacitance 12 pF
Inputleakagecurrent –1 1 µA
DIGITALINPUT
Logicfamily,CMOS
1.2V£ VDD<1.6V 0.7· VDD 3.6
1.6V£ VDD<1.8V 0.7· VDD 3.6
VIH Inputlogichighlevel 1.8V£ VDD<2.5V 0.7· VDD 3.6 V
2.5V£ VDD£ 3.6V 2 3.6
(1) LSB=LeastSignificantBIt
(2) Thedifferenceinthefirstcodetransition000...000to000...001fromtheidealvalueofGND+1LSB.
(3) Thedifferenceinthelastcodetransition011...111to111...111fromtheidealvalueofV -1LSBwiththeoffseterrorremoved.
DD
(4) Theabsolutedifferencefromtheidealtransferfunctionoftheconverter.ThisspecificationissimilartoINLerrorexcepttheeffectsof
offseterrorandgainerrorareincluded.
(5) The2ndthrough10thharmonicsareusedtodetermineTHD.
(6) Inputfrequencywheretheamplitudeofthedigitizedsignalhasdecreasedby0.1dBor3dB.
(7) Idealinputspanwhichdoesnotincludegainoroffseterrors.
5
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7867 (continued)
At–40(cid:176) Cto85(cid:176) C,f =240KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =120KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
1.2V£ VDD<1.6V –0.2 0.2· VDD
1.6V£ VDD<1.8V –0.2 0.2· VDD
VIL Inputlogiclowlevel 1.8V£ VDD<2.5V –0.2 0.3· VDD V
2.5V£ VDD£ 3.6V –0.2 0.8
ISCLK SCLKpinleakagecurrent Digitalinput=0VorVDD –1 0.02 1 µA
ICS CSpinleakagecurrent – 1 µA
CIN Digitalinputpincapacitance 10 pF
DIGITALOUTPUT
VOH Outputlogichighlevel ISOURCE=200µA VDD–0.2 VDD V
VOL Outputlogiclowlevel ISINK=200µA 0 0.2 V
ISDO SDOpinleakagecurrent Floatingoutput –1 1 µA
Digitaloutputpin
COUT capacitance Floatingoutput 10 pF
Dataformat,straightbinary
POWERSUPPLYREQUIREMENTS
VDD Supplyvoltage 1.2 3.6 V
fSAMPLE=240KSPS,fSCLK=3.4MHz,VDD=3.6V 420 500
µA
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=3.6V 172
Supplycurrent, DigitalInputs=0V fSAMPLE=240KSPS,fSCLK=3.4MHz,VDD=1.6V 261 330
IDD normaloperation orVDD fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=1.6V 107 µA
fSAMPLE=120KSPS,fSCLK=1.7MHz,VDD=1.2V 202 250
µA
fSAMPLE=50KSPS,fSCLK=1.7MHz,VDD=1.2V 83
IDD Power-downmode SCLKonoroff 0.008 0.3 µA
POWERDISSIPATION
fSAMPLE=240KSPS,fSCLK=3.4MHz,VDD=3.6V 1.51 1.80
Normaloperation fSAMPLE=240KSPS,fSCLK=3.4MHz,VDD=1.6V 0.42 0.53 mW
fSAMPLE=120KSPS,fSCLK=1.7MHz,VDD=1.2V 0.24 0.30
Power-downmode SCLKonoroff,VDD=3.6V 1.08 µW
TEMPERATURERANGE
Specifiedperformance –40 85 (cid:176)C
6
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7868
At–40(cid:176) Cto85(cid:176) C,f =280KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =140KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
SYSTEMPERFORMANCE
Resolution 8 Bits
Nomissingcodes 8 Bits
Integrallinearity –0.5 0.5 LSB(1)
Differentiallinearity –0.5 0.5 LSB
Offseterror(2) 1.2V£ VDD<1.6V –0.5 0.5 LSB
1.6V£ VDD£ 3.6V –0.5 0.5
Gainerror(3) 1.2V£ VDD<1.6V –0.5 0.5 LSB
1.6V£ VDD£ 3.6V –0.5 0.5
Totalunadjustederror(4) 1.2V£ VDD<1.6V –1 1 LSB
1.6V£ VDD£ 3.6V –1 1
SAMPLINGDYNAMICS(SeeTimingCharacteristicsSection)
tCONVERT Conversiontime fSCLK=3.4MHz,9SCLKcycles 2.647 µs
tSAMPLE Acquisitiontime fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 0.64 µs
fSAMPLE Throughputrate fSCLK=3.4MHz,1.6V£ VDD£ 3.6V 280 KSPS
Aperturedelay 10 ns
Aperturejitter 40 ps
DYNAMICCHARACTERISTICS
Signal-to-noise fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 49
SINAD dB
anddistortion fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 49 49.4
fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 49.4
SNR Signal-to-noiseratio dB
fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 49.8
Totalharmonic fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V –65
THD dB
distortion(5) fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V –72 -66
Spuriousfreedynamic fSAMPLE=100KSPS,fIN=30kHz,1.2V£ VDD<1.6V 67
SFDR dB
range fSAMPLE=200KSPS,fIN=30kHz,1.6V£ VDD£ 3.6V 66 67
At0.1dB,1.2V£ VDD<1.6V 2
Full-powerbandwidth(6) At0.1dB,1.6V£ VDD£ 3.6V 4 MHz
At3dB,1.2V£ VDD<1.6V 3
At3dB,1.6V£ VDD£ 3.6V 8
ANALOGINPUT
Full-scaleinputspan(7) VIN–GND 0 VDD V
CS Inputcapacitance 12 pF
Inputleakagecurrent –1 1 µA
DIGITALINPUT
Logicfamily,CMOS
1.2V£ VDD<1.6V 0.7· VDD 3.6
1.6V£ VDD<1.8V 0.7· VDD 3.6
VIH Inputlogichighlevel 1.8V£ VDD<2.5V 0.7· VDD 3.6 V
2.5V£ VDD£ 3.6V 2 3.6
(1) LSB=LeastSignificantBIt
(2) Thedifferenceinthefirstcodetransition000...000to000...001fromtheidealvalueofGND+1LSB.
(3) Thedifferenceinthelastcodetransition011...111to111...111fromtheidealvalueofV -1LSBwiththeoffseterrorremoved.
DD
(4) Theabsolutedifferencefromtheidealtransferfunctionoftheconverter.ThisspecificationissimilartoINLerrorexcepttheeffectsof
offseterrorandgainerrorareincluded.
(5) The2ndthrough10thharmonicsareusedtodetermineTHD.
(6) Inputfrequencywheretheamplitudeofthedigitizedsignalhasdecreasedby0.1dBor3dB.
(7) Idealinputspanwhichdoesnotincludegainoroffseterrors.
7
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
SPECIFICATIONS, ADS7868 (continued)
At–40(cid:176) Cto85(cid:176) C,f =280KSPSandf =3.4MHzif1.6V£ V £ 3.6V;f =140KSPSandf =1.7MHzif
SAMPLE SCLK DD SAMPLE SCLK
1.2V£ V <1.6V(unlessotherwisenoted)
DD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
1.2V£ VDD<1.6V –0.2 0.2· VDD
1.6V£ VDD<1.8V –0.2 0.2· VDD
VIL Inputlogiclowlevel 1.8V£ VDD<2.5V –0.2 0.3· VDD V
2.5V£ VDD£ 3.6V –0.2 0.8
ISCLK SCLKpinleakagecurrent Digitalinput=0VorVDD –1 0.02 1 µA
ICS CSpinleakagecurrent – 1 µA
Digitalinputpin
CIN capacitance 10 pF
DIGITALOUTPUT
VOH Outputlogichighlevel ISOURCE=200µA VDD–0.2 VDD V
VOL Outputlogiclowlevel ISINK=200µA 0 0.2 V
ISDO SDOpinleakagecurrent Floatingoutput –1 1 µA
Digitaloutputpin
COUT capacitance Floatingoutput 10 pF
Dataformat,straight
binary
POWERSUPPLYREQUIREMENTS
VDD Supplyvoltage 1.2 3.6 V
fSAMPLE=280KSPS,fSCLK=3.4MHz,VDD=3.6V 439 500
µA
fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=3.6V 154
Supplycurrent, DigitalInputs=0V fSAMPLE=280KSPS,fSCLK=3.4MHz,VDD=1.6V 264 330
IDD normaloperation orVDD fSAMPLE=100KSPS,fSCLK=3.4MHz,VDD=1.6V 93 µA
fSAMPLE=140KSPS,fSCLK=1.7MHz,VDD=1.2V 201 250
µA
fSAMPLE=50KSPS,fSCLK=1.7MHz,VDD=1.2V 70
IDD Power-downmode SCLKonoroff 0.008 0.3 µA
POWERDISSIPATION
fSAMPLE=280KSPS,fSCLK=3.4MHz,VDD=3.6V 1.58 1.8
Normaloperation fSAMPLE=280KSPS,fSCLK=3.4MHz,VDD=1.6V 0.42 0.53 mW
fSAMPLE=140KSPS,fSCLK=1.7MHz,VDD=1.2V 0.24 0.3
Power-downmode SCLKonoroff,VDD=3.6V 1.08 µW
TEMPERATURERANGE
Specifiedperformance –40 85 (cid:176)C
8
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
TIMING REQUIREMENTS(1)(2)
At–40°Cto85°C,f =3.4MHzif1.6V£ V £ 3.6V;f =1.7MHzif1.2V£ V <1.6V,50-pFLoadonSDOPin,
SCLK DD SCLK DD
unlessotherwisenoted
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
tsample Sampletime tSU(CSF-FSCLKF)+2· tC(SCLK) µs
ADS7866 13· tC(SCLK)
tconvert Conversiontime ADS7867 11· tC(SCLK) µs
ADS7868 9· tC(SCLK)
1.2V£ VDD<1.6V See(3) 100
1.6V£ VDD<1.8V See(3) 100
tC(SCLK) Cycletime 1.8V£ VDD<2.5V See(3) 50 µs
2.5V£ VDD£ 3.6V See(3) 6.7
tWH(SCLK) Pulseduration 0.4· tC(SCLK) 0.6· tC(SCLK) ns
tWL(SCLK) Pulseduration 0.4· tC(SCLK) 0.6· tC(SCLK) ns
1.2V£ VDD<1.6V 192
tSU(CSF-FSCLKF) Setuptime 1.6V£ VDD<1.8V 55 ns
1.8V£ VDD£ 3.6V 55
1.2V£ VDD<1.6V 65
tD(CSF-SDOVALID) Delaytime 1.6V£ VDD<1.8V 55 ns
1.8V£ VDD£ 3.6V 55
1.2V£ VDD<1.6V 20
tH(SCLKF-SDOVALID) Holdtime 1.6V£ VDD<1.8V 10 ns
1.8V£ VDD£ 3.6V 10
1.2V£ VDD<1.6V 140
tD(SCLKF-SDOVALID) Delaytime 1.6V£ VDD<1.8V 140 ns
1.8V£ VDD£ 3.6V 140
1.2V£ VDD<1.6V 10 80
tDIS(EOC-SDOZ) Disabletime 1.6V£ VDD<1.8V 7 60 ns
1.8V£ VDD£ 3.6V 7 60
1.2V£ VDD<1.6V 20
tWH(CS) Pulseduration 1.6V£ VDD<1.8V 10 ns
1.8V£ VDD£ 3.6V 10
1.2V£ VDD<1.6V 20
tSU(LSBZ-CSF) Setuptime 1.6V£ VDD<1.8V 10 ns
1.8V£ VDD£ 3.6V 10
(1) Allinputsignalsarespecifiedwitht =t =5ns(10%to90%ofV )andtimedfromavoltagelevelof(V +V )/2.
r f DD IL IH
(2) SeetimingdiagraminFigure1.
(3) Mint isdeterminedbytheMint ofthespecificresolutionandsupplyvoltage.SeeAcquisitionTime,ConversionTime,and
C(SCLK) SAMPLE
TotalCycleTimesectionforfurtherdetails.
HOLD tC(SCLK) EOC Last SCLK=16for ADS7866
14for ADS7867
1 2 3 4 5 tWH(6SCLK) 7 8 9 10 111642 12for ADS7868 1 tSU(2CSF−FSCLKF)
SCLK
tSU(CSF−FSCLKF) tWL(SCLK) tWH(CS)
CS
tSAMPLE tCONVERT tSU(LSBZ−CSF)
tH(SCLKF−SDOVALID) tDIS(EOC−SDOZ)
tD(CSF−SDOVALID) tD(SCLKF−SDOVALID) tD(CSF−SDOVALID)
SDO Hi−Z Hi−Z
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
“0” “0” “0” “0” LSB “0” “0” “0”
Auto Power−Down Auto Power−Down
tCYCLE
Figure1.TimingDiagram
9
ADS7866
ADS7867
ADS7868
www.ti.com
SLAS465–JUNE2005
PIN CONFIGURATION
ADS7866/67/68
DBV PACKAGE
(TOP VIEW)
REF/V 1 6 CS
DD
GND 2 5 SDO
VIN 3 4 SCLK
TERMINALFUNCTIONS
TERMINAL
DESCRIPTION
NAME NO.
REF/V 1 Externalreferenceinputandpowersupply
DD
GND 2 Groundforsignalandpowersupply.Allanaloganddigitalsignalsarereferredwithrespecttothispin.
VIN 3 Analogsignalinput
SCLK 4 Serialclockinput.Thisclockisusedforclockingdataout,anditisthesourceofconversionclock.
Thisistheserialdataoutputoftheconversionresult.TheserialstreamcomeswithMSBfirst.TheMSBisclockedout
(changed)onthefallingedgeoneSCLKafterthesamplingperiodends.ThisresultsinfourleadingzerosafterCS
SDO 5
becomesactive.SDOis3-statedonceallthevalidbitsareclockedout(12forADS7866,10forADS7867,and8for
ADS7868).
Thisisanactivelowinputsignal.ItisusedasachipselecttogatetheSCLKinput,toinitiateaconversion,andto
CS 6
frameoutputdata.
10