12-BITS, 125/105/80/65 MSPS ADC WITH DDR - Texas Instruments

67 Pages·2016·2.36 MB·English

ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
FEATURES
1
• MaximumSampleRate:125MSPS DESCRIPTION
• 12-BitResolutionwithNo MissingCodes ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)
• 3.5dBCoarseGainandupto6dB is a family of 12-bit A/D converters with sampling
frequencies up to 125 MSPS. It combines high
ProgrammableFineGainforSNR/SFDR
performance and low power consumption in a
Trade-Off
compact 32 QFN package. Using an internal high
• ParallelCMOS andDoubleDataRate (DDR) bandwidth sample and hold and a low jitter clock
LVDSOutputOptions buffer helps to achieve high SNR and high SFDR
• SupportsSine,LVCMOS,LVPECL, LVDSClock evenathigh input frequencies.
InputsandClockAmplitude Downto400mVPP It features coarse and fine gain options that are used
• ClockDutyCycleStabilizer to improve SFDR performance at lower full-scale
• InternalReferencewithSupportforExternal analoginput ranges.
Reference The digital data outputs are either parallel CMOS or
• NoExternal DecouplingRequiredfor DDR LVDS (Double Data Rate). Several features
exist to ease data capture such as — controls for
References
output clock position and output buffer drive strength,
• ProgrammableOutputClock Positionand
and LVDS current and internal termination
DriveStrengthtoEaseData Capture
programmability.
• 3.3VAnalog and1.8V to3.3VDigitalSupply
The output interface type, gain, and other functions
• 32-QFNPackage(5mm· 5mm) are programmed using a 3-wire serial interface.
• PinCompatible12-BitFamily(ADS612X) Alternatively, some of these functions are configured
using dedicated parallel pins so that the device
APPLICATIONS comesupinthedesiredstateafterpower-up.
• WirelessCommunicationsInfrastructure ADS612X includes internal references, while
• SoftwareDefinedRadio eliminating the traditional reference pins and
• PowerAmplifierLinearization associated external decoupling. External reference
modeisalsosupported.
• 802.16d/e
• TestandMeasurementInstrumentation The devices are specified over the industrial
temperaturerange(–40(cid:176) Cto85(cid:176) C).
• HighDefinition Video
• MedicalImaging
• RadarSystems
ADS612XPerformanceSummary
ADS6125 ADS6124 ADS6123 ADS6122
F =10MHz(0dBgain) 90 91 93 95
in
SFDR,dBc
F =170MHz(3.5dBgain) 78 82 83 84
in
F =10MHz(0dBgain) 71.1 71.3 71.5 71.6
in
SINAD,dBFS
F =170MHz(3.5dBgain) 67.6 69.1 69.2 69.8
in
Power,mW 417 374 318 285
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2008,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
D D
D D D N
D N V G
V G R R
A A D D
CLKP CLOCK CLKOUTP
CLKM GEN CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
INP Digital
12-Bit Encoder D6_D7_P
SHA
ADC and
D6_D7_M
INM Serializer
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
Control
VCM Reference
Interface
ADS612X
LVDS MODE
T K N A N
E L E T D
S C S A P
E S D
R S
ADS61XXFAMILY
125MSPS 105MSPS 80MSPS 65MSPS
ADS614X
ADS6145 ADS6144 ADS6143 ADS6142
14Bits
ADS612X
ADS6125 ADS6124 ADS6123 ADS6122
12Bits
2 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED
PACKAGE- PACKAGE PACKAGE ORDERING
PRODUCT TEMPERATURE TRANSPORTMEDIA
LEAD DESIGNATOR MARKING NUMBER
RANGE
ADS6125IRHBT TapeandReel,small
ADS6125 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6125
ADS6125IRHBR TapeandReel,large
ADS6124IRHBT TapeandReel,small
ADS6124 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6124
ADS6124IRHBR TapeandReel,large
ADS6123IRHBT TapeandReel,small
ADS6123 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6123
ADS6123IRHBR TapeandReel,large
ADS6122IRHBT TapeandReel,small
ADS6122 QFN-32(2) RHB –40(cid:176) Cto85(cid:176) C AZ6122
ADS6122IRHBR TapeandReel,large
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.q =34(cid:176) C/W(0LFMairflow),
JA
q =30(cid:176) C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3in· 3in(7.62cm·
JC
7.62cm)PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3to3.9 V
V
I
Supplyvoltagerange,DRVDD –0.3to3.9 V
VoltagebetweenAGNDandDRGND –0.3to0.3 V
VoltagebetweenAVDDtoDRVDD –0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) –0.3to2 V
Voltageappliedtoanaloginputpins,INPandINM –0.3tominimum(3.6,AVDD+0.3) V
Voltageappliedtoanaloginputpins,CLKPandCLKM –0.3to(AVDD+0.3) V
T Operatingfree-airtemperaturerange –40to85 (cid:176) C
A
T Operatingjunctiontemperaturerange 125 (cid:176) C
J
T Storagetemperaturerange –65to150 (cid:176) C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3 3.3 3.6 V
CMOSInterface 1.65 1.8to3.3 3.6 V
DRVDD Outputbuffersupplyvoltage (1)
LVDSInterface 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
pp
V Inputcommon-modevoltage 1.5±0.1 V
IC
VoltageappliedonVCMinexternalreferencemode 1.45 1.5 1.55 V
CLOCKINPUT
ADS6125 1 125
ADS6124 1 105
F Inputclocksamplerate MSPS
S
ADS6123 1 80
ADS6122 1 65
Sinewave,ac-Coupled 0.4 1.5
Inputclockamplitudedifferential LVPECL,ac-Coupled ±0.8
V
(VCLKP–VCLKM) LVDS,ac-Coupled ±0.35 pp
LVCMOS,ac-Coupled 3.3
InputClockdutycycle 35% 50% 65%
DIGITALOUTPUTS
ForC ≤5pFandDRVDD≥2.2 DEFAULT
LOAD
V strength
Outputbufferdrivestrength (2) ForCLOAD>5pFandDRVDD≥2.2 MAXIMUM
V strength
MAXIMUM
ForDRVDD<2.2V
strength
CMOSInterface,maximumbuffer 10
strength
Maximumexternalloadcapacitancefromeach LVDSInterface,withoutinternal 5
C pF
LOAD outputpintoDRGND termination
LVDSInterface,withinternal 10
termination
R Differentialloadresistance(external)betweentheLVDSoutputpairs 100 Ω
LOAD
T Operatingfree-airtemperature -40 85 (cid:176) C
A
(1) Foreasymigrationtonextgeneration,highersamplingspeeddevices(>125MSPS),use1.8VDRVDDsupply.
(2) SeeOutputBufferStrengthProgrammabilityinapplicationsection
4 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6125 ADS6124 ADS6123 ADS6122
PARAMETER FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 12 12 12 12 Bits
ANALOGINPUT
Differentialinputvoltagerange 2 2 2 2 VPP
Differentialinputresistance(atdc)
>1 >1 >1 >1 MΩ
seeFigure91
Differentialinputcapacitance
7 7 7 7 pF
seeFigure92
Analoginputbandwidth 450 450 450 450 MHz
Analoginputcommonmodecurrent 180 151 114 92 m A
(perinputpinofeachADC)
REFERENCEVOLTAGES
VREFB Internalreferencebottomvoltage 1 1 1 1 V
VREFT Internalreferencetopvoltage 2 2 2 2 V
ΔVREF Internalreferenceerror -20 ±5 20 -20 ±5 20 -20 ±5 20 -20 ±5 20 mV
(VREFT–VREFB)
VCM Commonmodeoutputvoltage 1.5 1.5 1.5 1.5 V
DCACCURACY
Nomissingcodes Specified Specified Specified Specified
EO Offseterror -10 ±2 10 -10 ±2 10 -10 ±2 10 -10 ±2 10 mV
Offseterrortemperaturecoefficient 0.05 0.05 0.05 0.05 mV/(cid:176)C
Therearetwosourcesofgainerror–internalreferenceinaccuracyandchannelgainerror
EGREF Gainerrorduetointernalreference -1 0.25 1 -1 0.25 1 -1 0.25 1 -1 0.25 1 %FS
inaccuracyalone,(ΔVREF/2)%
EGCHAN Gainerrorofchannelalone(1) -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 %FS
Channelgainerrortemperature 0.005 0.005 0.005 0.005 Δ%/(cid:176)C
coefficient
DNL Differentialnonlinearity -0.75 ±0.6 2 -0.75 ±0.6 2 -0.75 ±0.5 2 -0.75 ±0.5 2 LSB
INL Integralnonlinearity -2 ±1 2 -2 ±1 2 -2 ±1 2 -2 ±1 2 LSB
POWERSUPPLY
IAVDD Analogsupplycurrent 123 110 94 84 mA
Digitalsupplycurrent,CMOS
interface
IDRVDD DRVDD=1.8V 6.1 5.4 4.5 4.0 mA
Noloadcapacitance,FIN=2MHZ(2)
Digitalsupplycurrent,LVDSinterface
IDRVDD DRVDD=3.3V 42 42 42 42 mA
With100Ωexternaltermination
Totalpower,CMOS 417 625 374 525 318 440 285 400 mW
Globalpowerdown 30 60 30 60 30 60 30 60 mW
(1) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
(2) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequencyandtheloadcapacitanceonoutputpins(seeFigure84).
Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6125 ADS6124 ADS6123 ADS6122
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
DYNAMICACCHARACTERISTICS
Fin=10MHz 71.3 71.4 71.6 71.7
Fin=50MHz 68.5 71.1 71.1 69 71.4 71.5
Fin=70MHz 70.9 68.5 71 71.3 69 71.5
SNR 0dBGain 69.5 70 70.3 70.6
Signaltonoise Fin=170 dBFS
ratio,CMOS MHz 3.5dBCoarse 68.7 69.4 69.7 69.9
gain
0dBGain 68.6 69.2 69.6 69.9
Fin=230
MHz 3.5dBCoarse 67.9 68.6 69.1 69.4
gain
Fin=10MHz 71.5 71.5 71.8 71.8
Fin=50MHz 68.5 71.4 71.3 69 71.5 71.6
Fin=70MHz 71.3 68.5 71.3 71.5 69 71.6
SNR 0dBGain 70.3 70.3 70.6 70.7
Signaltonoise Fin=170 dBFS
ratio,LVDS MHz 3.5dBCoarse 69.8 69.8 70.1 70.1
gain
0dBGain 69.6 69.6 70 70.1
Fin=230
MHz 3.5dBCoarse 69 69 69.5 69.6
gain
Fin=10MHz 71.1 71.3 71.5 71.6
Fin=50MHz 68 70.3 70.7 68.5 71.3 71.4
Fin=70MHz 70.4 68 70.9 70.9 68.5 71.4
SINAD
Signaltonoise 0dBGain 67.7 69.5 69.6 70.2
anddistortion Fin=170 dBFS
ratio MHz 3.5dBCoarse 67.6 69.1 69.2 69.8
gain
CMOS
0dBGain 66.6 68 68.9 69.1
Fin=230
MHz 3.5dBCoarse 66.3 68 68.6 69
gain
Fin=10MHz 71.5 71.5 71.7 71.7
Fin=50MHz 70.6 70.7 71.4 71.5
Fin=70MHz 71 71 71.1 71.5
SINAD
Signaltonoise 0dBGain 69.1 69.7 70.1 70.3
anddistortion Fin=170 dBFS
ratio MHz 3.5dBCoarse 69.3 69.5 69.9 70
gain
LVDS
0dBGain 68.2 68.1 69.4 69.1
Fin=230
MHz 3.5dBCoarse 68.3 68.3 69.2 69.1
gain
ENOB Fin=50MHz 11 11.4 11 11.55
Effective Bits
numberofbits Fin=70MHz 11 11.5 11 11.56
Fin=10MHz 90 91 93 95
Fin=50MHz 76 80 83 79 89 89
Fin=70MHz 84 76 84 84 79 86
SFDR 0dBGain 76 80 81 82
Spuriousfree Fin=170 dBc
dynamicrange MHz 3.5dBCoarse 78 82 83 84
gain
0dBGain 75 77 79 79
Fin=230
MHz 3.5dBCoarse 76 79 81 82
gain
6 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode,appliestoCMOSandLVDSinterfaces,unlessotherwisenoted.
ADS6125 ADS6124 ADS6123 ADS6122
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin=10MHz 88.5 90 91.5 93
Fin=50MHz 73 79.5 82.5 76 88 88
Fin=70MHz 82 73 83 83 76 85
THD 0dBGain 73.5 79 78 80
Totalharmonic Fin=170 dBc
distortion MHz 3.5dBCoarse 75 81 79 82
gain
0dBGain 71.5 75.5 76 76
Fin=230
MHz 3.5dBCoarse 72.5 77.5 78 78.5
gain
Fin=10MHz 96 96 97 98
Fin=50MHz 76 95 96 79 96 96
Fin=70MHz 91 76 92 93 79 93
HD2
0dBGain 81 83 83 86
Second Fin=170 dBc
harmonic MHz 3.5dBCoarse 82 84 84 87
distortion gain
0dBGain 75 79 80 79
Fin=230
MHz 3.5dBCoarse 76 81 81 81
gain
Fin=10MHz 90 91 93 95
Fin=50MHz 76 80 83 79 89 89
Fin=70MHz 84 76 84 84 79 86
HD3 0dBGain 76 80 81 82
Thirdharmonic Fin=170 dBc
distortion MHz 3.5dBCoarse 78 82 83 84
gain
0dBGain 75 77 79 79
Fin=230
MHz 3.5dBCoarse 76 79 81 82
gain
Fin=10MHz 93 94 96 97
Fin=50MHz 92 90 93 96
Worstspur Fin=70MHz 91 90 92 95
(Otherthan dBc
Fin=170
HD2,HD3) 90 89 89 91
MHz
Fin=230
90 88 89 90
MHz
IMD
2-Tone F1=185MHz,F2=190MHz
83 82 84 88 dBFS
intermodulation Eachtoneat-7dBFS
distortion
Recoverytowithin1%(offinal
Inputoverload clock
value)for6-dBoverloadwithsine 1 1 1 1
recovery cycles
waveinput
PSRR
ACPower For100mVppsignalonAVDD
35 35 35 35 dBc
supplyrejection supply
ratio
Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
DIGITAL CHARACTERISTICS(1)
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1AVDD=3.3V
ADS6125/ADS6124
PARAMETER TESTCONDITIONS
ADS6123/ADS6122
MIN TYP MAX UNIT
DIGITALINPUTS
PDN,SCLK,SEN&SDATA (2)
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 m A
Low-levelinputcurrent –33 m A
Inputcapacitance 4 pF
DIGITALOUTPUTS
CMOSINTERFACE,DRVDD=1.8to3.3V
High-leveloutputvoltage DRVDD V
Low-leveloutputvoltage 0 V
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eachoutputtoground
DIGITALOUTPUTS
LVDSINTERFACE,DRVDD=3.3V,I =3.5mA,R =100Ω (3)
O L
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
Outputdifferentialvoltage,|V | 225 350 mV
OD
V Outputoffsetvoltage,single-ended Common-modevoltageofOUTP,OUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eitheroutputtoground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) SCLK&SENfunctionasdigitalinputpinswhentheyareusedforserialinterfaceprogramming.Whenusedasparallelcontrolpins,
analogvoltageneedstobeappliedasperTable1&Table2.
(3) I ReferstotheLVDSbuffercurrentsetting,R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
8 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25(cid:176) C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40(cid:176) CtoT =85(cid:176) C,AVDD=
MIN MAX
DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,1.5V clockamplitude,C =5pF(2),I =3.5
PP L O
mA,R =100Ω (3),nointernaltermination,unlessotherwisenoted.
L
Fortimingsatlowersamplingfrequencies,seesectionOutputTimingsintheAPPLICATIONINFORMATIONofthisdata
sheet.
ADS6125 ADS6124 ADS6123 ADS6122
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Aperture
ta delay 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns
Aperture
tj jitter 150 150 150 150 fsrms
Fromglobalpower 15 50 15 50 15 50 15 50 m s
down
Wake-up
time Fromstandby 15 50 15 50 15 50 15 50 m s
(tovalid
Fromoutput CMOS 100 200 100 200 100 200 100 200 ns
data)
buffer
disable LVDS 200 500 200 500 200 500 200 500 ns
clock
Latency 9 9 9 9
cycles
DDRLVDSMODE(4),DRVDD=3.3V
Datavalid(6)to
Datasetup
tsu time(5) zero-crossof 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns
CLKOUTP
Zero-crossof
Datahold
th time(5) CbeLcKoOmUinTgPintovadliadt(a6) 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns
Inputclockrisingedge
Clock
zero-crosstooutput
tPDI propagation clockrisingedge 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns
delay
zero-cross
Dutycycleof
LVDSbit differentialclock,
clockduty (CLKOUTP- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55%
cycle CLKOUTM)
10≤Fs≤125MSPS
Risetimemeasured
Datarise
from–50mVto50mV
tr time, Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tf Datafall from50mVto–50mV
time
1≤Fs≤125MSPS
Risetimemeasured
tCLKRI Outputclock from–50mVto50mV
SE risetime, Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tCLKFA Outputclock from50mVto–50mV
LL falltime 1≤Fs≤125MSPS
PARALLELCMOSMODE,DRVDD=2.5Vto3.3V,defaultoutputbufferdrivestrength(7)
Datasetup Datavalid(8)to50%of
tsu time(5) CLKOUTrisingedge 2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns
50%ofCLKOUT
Datahold
th time(5) Rbeiscionmgiendggienvtoalidda(8ta) 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns
Clock Inputclockrisingedge
tPDI propagation zero-crossto50%of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns
delay CLKOUTrisingedge
(1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction.
(2) C istheEffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I ReferstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
(4) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) Datavalidreferstologichighof+100mVandlogiclowof–100mV.
(7) ForDRVDD<2.2V,itisrecommendedtouseexternalclockfordatacaptureandNOTthedeviceoutputclocksignal(CLKOUT).See
ParallelCMOSinterfaceinapplicationsection.
(8) Datavalidreferstologichighof2V(1.7V)andlogiclowof0.8V(0.7V)forDRVDD=3.3V(2.5V).
Copyright©2007–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122
ADS6125, ADS6124
ADS6123, ADS6122
www.ti.com
SLAS560A–OCTOBER2007–REVISEDMARCH2008
TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)
Fortimingsatlowersamplingfrequencies,seesectionOutputTimingsintheAPPLICATIONINFORMATIONofthisdata
sheet.
ADS6125 ADS6124 ADS6123 ADS6122
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Dutycycleofoutput
Outputclock
clock(CLKOUT) 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55%
dutycycle
10≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
Datarise
DRVDD
tr time, Falltimemeasured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
tf Datafall from80%to20%of
time
DRVDD
1≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
tCLKRI Outputclock DRVDD
SE risetime, Falltimemeasured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns
tCLKFA Outputclock from80%to20%of
LL falltime DRVDD
1≤Fs≤125MSPS
10 SubmitDocumentationFeedback Copyright©2007–2008,TexasInstrumentsIncorporated
ProductFolderLink(s):ADS6125,ADS6124ADS6123,ADS6122