12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface

42 Pages·2016·0.9 MB·English

ADS61JB23
www.ti.com.cn ZHCSAM6 –DECEMBER2012
具具有有 JESD204A 输输出出接接口口的的 12 位位输输出出缓缓冲冲 80 每每秒秒百百万万次次采采样样 (MSPS) 模模
数数转转换换器器 (ADC)
查查询询样样品品:ADS61JB23
特特性性 应应用用范范围围
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• 输输出出接接口口：： • 无无线线基基站站基基础础设设施施
– 单单信信道道和和双双信信道道接接口口 • 测测试试和和测测量量仪仪器器
– 1.6Gbps 的的最最大大数数据据速速率率
– 符符合合JESD204A技技术术规规范范
– 可可在在2mA 至至32mA之之间间对对电电流流进进行行设设定定的的电电
流流模模式式逻逻辑辑(CML)输输出出
• 功功率率耗耗散散：：
– 单单信信道道模模式式下下，，80MSPS 时时为为440mW
– 功功率率等等级级随随着着时时钟钟速速率率下下降降
• 输输入入接接口口：：经经缓缓冲冲的的模模拟拟输输入入
• 71.7dBFS信信噪噪比比(SNR)（（在在70MHzIF 时时））
• 模模拟拟输输入入满满量量程程范范围围(FSR)：：2Vpp
• 外外部部和和内内部部（（经经调调整整的的））基基准准支支持持
• 用用于于输输入入缓缓冲冲器器的的1.8V电电源源（（模模拟拟和和数数
字字）），，3.3V电电源源
• 可可编编程程数数字字增增益益：：0dB-6dB
• 标标准准偏偏移移二二级级制制或或补补码码输输出出
• 封封装装：：
– 6mmx6mm 四四方方扁扁平平无无引引线线(QFN)-40封封装装
说说明明
ADS61JB23是一款高性能、低功耗、单通道模数转换器，此转换器具有一个集成的JESD204A输出接口。采用
6mmx6mmQFN封装，并具有单信道和双信道输出模式，ADS61JB23 提供了空前的紧凑性。输出接口与
JESD204A标准兼容，并具有一个额外的模式（符合IEEE 标准802.3-2002第3 部分，第36.2.4.12条），以实
现与TITLK串化解串(SERDES) 接收器系列产品的无缝对接。同样引人注目的是其包含一个片载模拟输入缓冲
器，从而提供了采样/保持开关间的隔离以及更高、更加持续的输出阻抗。
ADS61JB23可在工业温度范围（-40°C至85°C）内工作。
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Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2012,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not EnglishDataSheet:SLOS755
necessarilyincludetestingofallparameters.
ADS61JB23
ZHCSAM6 –DECEMBER2012 www.ti.com.cn
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
FUNCTIONALBLOCKDIAGRAM
AVDD_3 V AVDD AGND CLKP CLKM DRVDD DRGND SYNC~PSYNC~M IOVDD
CLOCKGEN
PLL CML
10X/20X OUTPUTS
INP ADC_OUTP<0>
ADC_OUTM<0>
Buffer 12 bitADC JESD204A
Digital
ADC_OUTP<1>
INM
ADC_OUTM<1>
Signal level
OVR
detect
DETECT<3:0>
VCM REFERENCE CONTROL
INTERFACE
CMOS
OUTPUTS
T R E 01 F N A
E C L TT E D N
S S D SS R P A
RE _SERF0_ FALIGN_I DATA_TEDATA_TE DFS_EXT PDN_
K _ SS
L N
C E
S S
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ADS61JB23
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RHAPACKAGE
(TOPVIEW)
> > > >
<0> <1> <2> <3> TP<0 TM<0 TP<1 TM<1
T T T T U U U U
C C C C O O D O O
OVR DETE DETE DETE DETE ADC_ ADC_ OVD ADC_ ADC_
I
40 39 38 37 36 35 34 33 32 31
SYNC~M 1 30 DRVDD
Pad is connected to DRGND
SYNC~P 2 29 DRGND
DFS_EXTREF 3 28 SDOUT_TEST1
PDN_ANA 4 27 DRVDD
AVDD 5 26 RESET
4480QQFFNN
AGND 6 25 SCLK_SERF0_SCR
CLKP 7 24 SDATA_TEST0
CLKM 8 23 SEN_FALIGN_IDLE
AGND 9 22 AVDD
VCM 10 21 PDN
11 12 13 14 15 16 17 18 19 20
D P M D D D V D E D
N N N N D N 3 D D D
AG I I AG AV AG DD_ AV MO FAV
V
A
PINFUNCTIONS
PIN
DESCRIPTION
NAME NO.
ADC_OUTM<1> 31 CMLoutputLane2–Negativeoutput
ADC_OUTM<0> 34 CMLoutputLane1–Negativeoutput
ADC_OUTP<1> 32 CMLoutputLane2–Positiveoutput
ADC_OUTP<0> 35 CMLoutputLane1–Positiveoutput
5,6,9,11,14,
AGND Analogground
16,
AVDD 15,18,22 Analogsupply,1.8V
AVDD_3V 17 Analogsupplyforinputbuffer,3.3V
CLKM 8 Conversionclock–Negativeinput
CLKP 7 Conversionclock–Positiveinput
DRGND 29 Digitalground
DRVDD 27,30 Digitalsupply,1.8V
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PINFUNCTIONS(continued)
PIN
DESCRIPTION
NAME NO.
DETECT<3> 36
DETECT<2> 37 Signalleveldetectoutputpins:Canbeusedtoeitheroutputa4-bitADCcodewithlowlatencyorto
DETECT<1> 38 outputa16-levelRMSpowerestimate
DETECT<0> 39
DFS_EXTREF 3 4-levelanalogcontrolforDataFormatselectandInternal/Externalreferencemode
FAVDD 20 Fusesupply–connectexternallytoAVDD,1.8V
IOVDD 33 CMLbuffersupply–1.2Vto1.9V
INM 13 Analoginput-Negative
INP 12 Analoginput–Positive
MODE 19 4-levelcontrolforSerialinterface/Parallelinterfacemodesselection
OVR 40 Over-rangeoutput
PDN 21 FullchipPowerdown(alsoreferredtoasCompletePowerdownmode)
Analogsectionpowerdown,JESDinterfacestillactive.Thisisreferredtoasfastrecoverypowerdown
PDN_ANA 4
mode
RESET 26 ChipResetinput
SCLK_SERF0_ InSerialinterfacemode:SerialclockinputInparallelinterfacemode:4-levelcontrolforJESDmodes
25
SCR (single/duallane&scrambling)
SDATA_TEST0 24 InSerialinterfacemode:SerialdatainputInparallelinterfacemode:JESDtestmode
InSerialinterfacemode:Serialdataoutput(forregisterreadout)Inparallelinterfacemode:JESDtest
SDOUT_TEST1 28
mode
SEN_FALIGN_I InSerialinterfacemode:Serialenable(Chipselect)Inparallelinterfacemode:4-levelcontrolfor
23
DLE JESDmodes
SYNC~M 1 JESDSynchronizationrequest–Negativeinput
SYNC~P 2 JESDSynchronizationrequest–Positiveinput
Commonmodeoutputforsettinginputcommonmode:1.95V,Referenceinputinexternalreference
VCM 10
mode
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
AVDD –0.3to+2.2 V
DRVDD –0.3to+2.2 V
Supplyvoltagerange
IOVDD –0.3to+2.2 V
AVDD_3V –0.3to+3.9 V
VoltagebetweenAGNDandDRGND –0.3to+0.3 V
VoltageappliedtoexternalVCMpin –0.3to+2.2 V
Voltageappliedtoanaloginputpins –0.3tomin(3,AVDD_3V+0.3) V
Voltageappliedtodigitalinputpins –0.3toAVDD+0.3 V
Voltageappliedtoclockinputpins(2) –0.3toAVDD+0.3 V
TA Operatingfree-airtemperaturerange –40to85 °C
Peaksoldertemperature 260 °C
Junctiontemperature 105 °C
(1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay
degradedevicereliability.
(2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMislessthan|0.3V|.
ThispreventstheESDprotectiondiodesattheclockinputpinsfromturningon.
4 Copyright©2012,TexasInstrumentsIncorporated
ADS61JB23
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THERMAL INFORMATION
ADS61JB23
THERMALMETRIC(1) UNITS
QFN40PIN
θ Junction-to-ambientthermalresistance 30.7
JA
θ Junction-to-case(top)thermalresistance 17
JCtop
θ Junction-to-boardthermalresistance 5.7
JB
°C/W
ψ Junction-to-topcharacterizationparameter 0.2
JT
ψ Junction-to-boardcharacterizationparameter 5.7
JB
θ Junction-to-case(bottom)thermalresistance 1
JCbot
(1) 有关传统和新的热度量的更多信息，请参阅IC封装热度量应用报告，SPRA953。
RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
SUPPLIES,ANALOGINPUTSANDREFERENCEVOLTAGES
Analogsupplyvoltage,AVDD 1.7 1.8 1.9 V
Digitalsupplyvoltage,DRVDD 1.7 1.8 1.9 V
CMLbuffersupplyvoltage,IOVDD 1.2 1.8 1.9 V
Analogbuffersupplyvoltage,AVDD_3V 3.0 3.3 3.6 V
Differentialinputvoltagerange 2 V
PP
VCM
Inputcommon-modevoltage V
±0.05
VCM(output)–Internalreferencemode(1) 1.95 V
VCM(input)–Externalreferencemode 1.4 V
CLOCKINPUT
InputclockrateinJESD204Asinglelanemode 15.625 80 MSPS
InputclockrateinJESD204Aduallanemode 31.25 80 MSPS
Sinewave,ac-coupled 0.2 3.0 V
PP
Inputclockamplitudedifferential(VCLKP- LVPECL,ac-coupled 1.6 VPP
VCLKM) LVDS,ac-coupled 0.7 VPP
CMOS,single-ended,ac-coupled 1.5 V
Inputclockdutycycle 35% 50% 65%
DIGITALOUTPUTS
20x
Outputdatarateinsingle-lanemode 312.5 (sample 1600 MBPS
rate)
10x
Outputdatarateindual-lanemode 312.5 (sample 800 MBPS
rate)
C MaximumexternalloadcapacitancefromeachpintoDRGND 5 pF
LOAD
R ExternalterminationfromeachoutputpintoIOVDD 50 Ω
LOAD
T Operatingfree-airtemperature -40 85 °C
A
HIGHSFDRMODE
Writeregister2h,value71htogetbestHD3forinputfrequenciesbetween150MHzto
250MHz.
(1) TypicalVCMreducesto1.85VafterHIGHSFDRMODEiswritten.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesat25°C,MINandMAXvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
1.8V,AVDD_3V=3.3V,DRVDD=1.8V,IOVDD=1.8V,Clockfrequency=80MSPS,50%clockdutycycle,–1dBFS
differentialanaloginput,internalreferencemode,CMLbuffercurrentsetting=16mA,unlessotherwisenoted.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
REFERENCEVOLTAGES–INTERNAL
VCManaloginputcommonmodevoltage(output) 1.95 V
VCMoutputcurrent(resultinginaVCMchangeof±50mV) 2.5 mA
REFERENCEVOLTAGES–EXTERNAL
VCMreferencevoltage(Input) 1.4±0.1 V
ANALOGINPUT
Differentialinputvoltagerange 2.0 Vpp
Differentialinputcapacitance 3 pF
Analoginputbandwidth 480 MHz
Analoginputcommonmoderange VCM±0.05 V
Analoginputcommonmodecurrent(perinputpin) 1.6 µA
DCACCURACY
Offseterror –20 20 mV
Duetointernalreference
–2.5 2.5 %FS
Gainerror inaccuracyalone
Duetochannelalone 5 %FS
Gainerrortemperaturecoefficient 0.006 mV/°C
ACPowerSupplyRejectionRatio,PSRR 50mV signalonAVDDsupply >30 dB
PP
POWERDOWNMODES
Completepowerdownmode 10 mW
Fastrecoverypowerdownmode 210 mW
Powerwithnoclock 115 mW
DNLdifferentialnonlinearity –0.7 ±0.3 0.8 LSB
INLintegralnonlinearity ±0.7 ±1.5 LSB
POWERSUPPLYCURRENTS
AVDDcurrent 105 122 mA
AVDD_3Vcurrent 40 51 mA
DRVDDcurrent 50 61 mA
IOVDDcurrent 16 21 mA
Totalpower 440 500 mW
DYNAMICPERFORMANCE(1)
IF=10MHz 80 dBc
SFDR
IF=185MHz 70 80 dBc
IF=10MHz 71.7 dBFs
SNR
IF=185MHz 68 70.5 dBFs
IF=10MHz 71.2 dBFs
SINAD
IF=185MHz 70.1 dBFs
IF=10MHz 80 dBc
HD3
IF=185MHz 70 80 dBc
IF=10MHz 100 dBc
HD2
IF=185MHz 70 80 dBc
IF=10MHz 90 dBc
Worstspur(excludingHD2,HD3)
IF=185MHz 81 87 dBc
(1) HIGHSFDRMODEisenabled.
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ADS61JB23
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DIGITAL CHARACTERISTICS
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS
High-levelinputvoltage 1.2 V
Low-levelinputvoltage 0.6 V
SEN 0
High-levelinputcurrent μA
SCLK,SDATA,RESET,PDN,PDN_ANA 10
SEN 10
Low-levelinputcurrent μA
SCLK,SDATA,RESET,PDN,PDN_ANA 0
DIGITALOUTPUTS(SDOUT)
DRVDD-
High-leveloutputvoltage DRVDD V
0.1
Low-leveloutputvoltage 0 0.1 V
CMLOUTPUTS–50ΩSINGLE-ENDEDEXTERNALTERMINATIONTOIOVDD
IOVDDsupplyrange 1.2 1.8 1.9 V
High-leveloutputvoltage IOVDD V
IOVDD-
Low-leveloutputvoltage V
0.4
Outputdifferentialvoltage,|VOD| 0.4 V
IOVDD-
Outputcommon-modevoltage,V V
OCM 0.2
Transmitterterminalsshortedtoanyvoltagebetween
Transmittershortcircuitcurrent -90 50 mA
–0.25Vand1.45V
Single-endedoutputimpedance 50 Ω
Unitinterval,UI 625 3200 UI
TotalJitter,T 0.35 p-pUI
J
Rise/falltimes 5pFsingle-endedloadcapacitancetoground 175 ps
WAKE-UP TIMING CHARACTERISTICS
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
TimetovaliddataaftercomingoutofCOMPLETEPOWERDOWNmode 50 μs
TimetovaliddataaftercomingoutofFASTRECOVERYPOWERDOWNmode 50 μs
Wake-uptime
TimetovaliddataaftercomingoutofSOFTWAREPOWERDOWNmode 10 μs
Timetovaliddataafterstoppingandrestartingtheinputclock 5 μs
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DETAILED DESCRIPTION
JESD204A OUTPUT INTERFACE
The 12-bit ADC output is padded with 4 zeros on the LSB side to form a 16-bit output. Two 8B10B codes are
formed–onefromthe8MSBsandtheotherfromthe6LSBsandthe2paddedzeros.
ADCOUT<11:4> ADCOUT<3:0>,0,0,0,0
8B10B code1 8B10B code2
MSB octet LSB octet
Figure1. MappingofADCOutputtoTwo8B10BCodes
The two octets can be either transmitted on the same lane (single lane interface) or on two lanes (dual lane
interface).Bydefault,thedeviceoperatesinsinglelaneinterface.
Conversion clock
(CLKP-CLKM)
CMLoutput Lane1
(ADC_OUTP<0>-
ADC_OUTM<0>) Dx.y Dx.y Dx.y Dx.y
(ADC data N,MSB octet) (ADC data N,LSB octet) (ADC data N+1,MSB octet) (ADC data N+1,LSB octet)
Figure 2. SingleLaneTiming
Conversion clock
(CLKP-CLKM)
CMLoutput Lane1
(ADC_OUTP<0>-
ADC_OUTM<0>) Dx.y Dx.y Dx.y Dx.y
(ADC data N,MSB octet) (ADC data N+1,MSB octet) (ADC data N+2,MSB octet) (ADC data N+3,MSB octet)
CMLoutput Lane2
(ADC_OUTP<1>-
ADC_OUTM<1>) Dx.y Dx.y Dx.y Dx.y
(ADC data N,LSB octet) (ADC data N+1,LSB octet) (ADC data N+2,LSB octet) (ADC data N+3,LSB octet)
Figure3. Dual LaneTiming
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ADS61JB23
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Thedetailedtimingdiagramintheduallanemodeisshownbelow:
N+22
N+2 N+3 N+4 N+21
N+1
Sample N+20
N
INPUT
SIGNAL
t
a
CLKP
INPUT
CLOCK
CLKM
20clock cycles* t
PDI
CMLOUTPUT
DATALANE 1
N-21 N-20 N-19 N-18 N-17 N-1 N N+1 N+2
CMLOUTPUT
DATALANE 2
N-21 N-20 N-19 N-18 N-17 N-1 N N+1 N+2
*This is theADC latency.At higher sampling frequencies,t >1clock cycle.
PDI
Then,overall latency=ADC latency+1.
Figure4. DataTimingDiagram-Dual LaneMode
PARAMETER 30MSPS 40MSPS 60MSPS 80MSPS
Aperturedelay–T 560ps 560ps 560ps 560ps
A
Aperturejitter(RMS)–T 125fs 125fs 125fs 125fs
J
Latency 20clocks 20clocks 20clocks 20clocks
t Datapropagationdelay 33.3ns 26.2ns 18.9ns 15.3ns
PDI
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Whenever there is a need to synchronize to the frame boundary of the output data stream, the receiver issues a
synchronization request through the SYNC~P, SYNC~M pins. Below diagram shows how the transmission
switches from normal data (D) to code group synchronization symbols K28.5 symbols during and after a
synchronizationrequest.
N+7 N+8 N+9
N+5 N+6
N+4
N+3
N+2
N+1
Sample
INPUT
N
SIGNAL
CLKP
INPUT
CLOCK
CLKM
t
CLK-INT
INTERNALCLOCK
FOR LATCHING SYNC~
(CLK_INT)
t
SYNC-SU
t
SYNC-H
SYNC~input
(SYNC~P)-(SYNC~M)
‘SYNC~active’latency=9clock cycles tSYNC-PDI
CMLOUTPUT
DATALANE1
N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 K28.5
CMLOUTPUT
DATALANE2
N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 K28.5
Figure5. SYNC~ACTIVETimingDiagram
Table1.SYNC~FallingEdgeTimingat80MSPS
PARAMETER DESCRIPTION TYP UNIT
Delayfrominputclockrisingedgetotherisingedgeoftheinternalclock
t 10.5 ns
CLK-INT (CLK_INT)usedtolatchfallingedgeofSYNC~
t SYNC~activeedgesetuptime MinimumdelayrequiredfromSYNC~fallingedgetoCLK_INTrisingedge 2 ns
SYNC-SU
t SYNC~activeedgeholdtime MinimumdelayrequiredfromCLK_INTrisingedgetoSYNC~fallingedge 2 ns
SYNC-H
SYNC~activelatency NumberofclocksforK28.5toappearattheoutputafteraSYNC~request 9 clocks
t SYNC~datapropagation Similartodatapropagationdelay 15.3 ns
SYNC-PDI
delay
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