10-bit 1 GS/s Single-Channel Asynchronous SAR ADC in 28 nm CMOS-Bulk Technology

54 Pages·2012·1.85 MB·English

10-bit 1 GS/s Single-Channel Asynchronous SAR ADC
in 28 nm CMOS-Bulk Technology

Ayça Akkaya

Master Thesis
2016

Supervised by
Prof. Yusuf Leblebici
Tuğba Demirci

Microelectronic Systems Laboratory STI/LSM
Electrical and Electronic Engineering Section
5 August 2016

Acknowledgements
First of all, I would like to thank Prof. Yusuf Leblebici for giving me the opportunity to
work at LSM during my Master’s education. Thanks to the opportunity that he provided, I
had a chance to involve in various projects including my master’s thesis which helped me
to improve myself and gain a great experience.
I also would like to thank Tuğba Demirci for supervising me and sharing her knowledge
with me during my thesis and all the other projects.
I am thankful to my Turkish friends in Lausanne for enjoyable activities and fun times we
had. Also, I would like to thank all my friends at LSM for providing such a nice working
environment.
I would like to thank Fırat Çelik for always supporting me and encouraging me. Finally, I
would like to thank my parents for all their support and love.

Lausanne, 05.08.2016 Ayça Akkaya

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Abstract
Low power consumption is one of the main design goals in recent electronic systems. Many
of those systems require analog-to-digital converters (ADCs) to convert the analog signals
to digital. Among the other ADC topologies, Successive-approximation-register (SAR)
ADCs are known for their low-power consumption and being suitable for deep submicron
CMOS technology nodes.
In this work, 10-bit single channel asynchronous SAR ADC is designed in 28nm CMOS-
Bulk technology. It exploits asynchronous operation in addition to two comparators work-
ing alternately in order to increase the sampling rate. Bootstrapped sampling switches pro-
vides better linearity. Binary weighted capacitive DAC with fractional reference voltages
is used for decreasing the number of capacitors within the DAC. For low-power consump-
tion, DAC utilizes an energy efficient switching sequence. In addition, StrongARM latches
are used as comparators for low-power operation and offset calibration is also included.
The designed 10-bit asynchronous SAR ADC runs at 500 MS/s and consumes 2.674mA at
0.9V power supply and achieves 58.76 dB SNDR and 9.468 bits ENOB near Nyquist rate.
Keywords
ADC, analog-to-digital-converter, SAR, successive approximation, charge redistribution,
asynchronous, alternate comparators, offset calibration.
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Contents
Acknowledgements ............................................................................................................. i
Abstract .............................................................................................................................. iii
Keywords ........................................................................................................................... iii
Contents .............................................................................................................................. v
List of Figures ................................................................................................................... vii
List of Tables ..................................................................................................................... ix
Introduction ........................................................................................... 1
1.1 Motivation ......................................................................................................... 1
1.2 Thesis Organization .......................................................................................... 2
Theoretical View of SAR ADCs ........................................................... 3
2.1 Traditional SAR ADC Architecture .................................................................. 3
2.2 Error Sources and Performance Metrics in SAR ADCs ................................... 6
Design and Implementation of Asynchronous SAR ADC ............... 11
3.1 Architecture Overview .................................................................................... 11
3.2 Building Blocks............................................................................................... 13
3.2.1 Sampling Switch .................................................................................... 13
3.2.2 Comparator with Offset Calibration ...................................................... 17
3.2.3 Capacitive DAC ..................................................................................... 20
3.2.4 SAR Logic ............................................................................................. 26
3.2.5 Asynchronous Clock Generator............................................................. 28
3.3 Layouts ............................................................................................................ 31
3.4 Simulation Results .......................................................................................... 33
Conclusion ............................................................................................ 39
4.1 Achieved Results............................................................................................. 39
4.2 Future Work .................................................................................................... 39
References ......................................................................................................................... 41
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List of Figures

Figure 1.1 FoMs vs. sampling rate plot (the data is taken from [1]). .............. 1
Figure 2.1 Block diagram of a SAR ADC. ..................................................... 3
Figure 2.2 Example SAR conversion (4 bits). ................................................ 4
Figure 2.3 Binary search algorithm of a 4-bit SAR ADC. ............................. 4
Figure 2.4 Charge redistribution SAR ADC (Single ended). ......................... 5
Figure 2.5 Ideal input-output characteristic of a 3-bit ADC and the
quantization noise. .......................................................................................... 6
Figure 2.6 Offset error in an ADC transfer function. ..................................... 7
Figure 2.7 Gain error in an ADC transfer function. ....................................... 7
Figure 2.8 DNL in an ADC transfer function. ................................................ 8
Figure 2.9 INL in an ADC transfer function. ................................................. 9
Figure 2.10 Non-monotonicity and missing code in an ADC transfer
function. .......................................................................................................... 9
Figure 3.1 Asynchronous SAR ADC............................................................ 12
Figure 3.2 Asynchronous SAR ADC timing sequence. ............................... 12
Figure 3.3 Transmission gate as a sampling switch. .................................... 13
Figure 3.4 On-resistance Ron vs. input voltage V graph for
in
Transmission Gate, PMOS and NMOS. ....................................................... 14
Figure 3.5 Bootstrapping scheme, (a) precharging phase, (b) sampling
phase, (c) implementation of gate bootstrapping with ideal switches. ......... 15
Figure 3.6 Bootstrapping waveforms. .......................................................... 15
Figure 3.7 Transistor level implementation of bootstrapped switch. ........... 16
Figure 3.8 StrongARM latch. ....................................................................... 17
Figure 3.9 Transient response of StrongARM latch outputs. ....................... 18
Figure 3.10 Comparator offset calibration circuit. ....................................... 19
Figure 3.11 CDAC topology, (a) CDACP, (b) CDACN. ............................. 21
Figure 3.12 Example waveforms of CDACP and CDACN outputs. ............ 22
Figure 3.13 CDAC topology with constant common mode. ........................ 23
Figure 3.14 Using fractional voltages to adjust the weight. ......................... 24
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Figure 3.15 CDAC switches, (a) switch circuit for 2 ≤ N ≤ 8, (b) switch
circuit for N=1, 0. ......................................................................................... 25
Figure 3.16 Error due to incomplete CDAC settling. ................................... 26
Figure 3.17 Memory cell. ............................................................................. 27
Figure 3.18 Memory block used for implementing the SAR logic. ............. 28
Figure 3.19 Asynchronous clock generator circuit. ...................................... 29
Figure 3.20 Adjustable delay circuit for asynchronous clock generation. ... 30
Figure 3.21 Layout of CDAC with bottom plate switches. .......................... 31
Figure 3.22 Layout of the memory block. .................................................... 31
Figure 3.23 Layout of the comparator with calibration differential pair. ..... 32
Figure 3.24 Top-level layout plan. ............................................................... 33
Figure 3.25 DNL and INL graphs................................................................ 34
Figure 3.26 Output Spectrum for fs=500MHz and fin=243.65MHz. ............ 34
Figure 3.27 SNDR vs. input amplitude. ....................................................... 35
Figure 3.28 ENOB vs. sampling frequency. ................................................. 36
Figure 3.29 ENOB vs. input frequency. ....................................................... 36

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