SOI Design: Analog, Memory and Digital Techniques

416 Pages·2001·21.35 MB·English

by  Andrew Marshall

SOI DESIGN
ANALOG, MEMORY
AND
DIGITAL TECHNIQUES
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SOI DESIGN
ANALOG, MEMORY
AND
DIGITAL TECHNIQUES
by
Andrew Marshall
&
Sreedhar Natarajan
Texas Instruments Incorporated
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48161-8
Print ISBN: 0-7923-7640-4
©2003 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
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SOI Design: Analog, Memory & Digital Techniques
To Judith, Amy and Elise for their enduring patience and encouragement.
-- Andrew Marshall
To my wife Chandra for her patience and support, my Parents, my brother
Sriram and his family, my wife’s family, and friends for their continued
encouragement.
-- Sreedhar Natarajan
v
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SOI Design: Analog, Memory & Digital Techniques
Table of Contents
Preface xix
Acknowledgements xxi
Chapter 1: Overview 1
1.1 Silicon on Insulator – a brief Introduction 1
1.2 Circuits and SOI 2
1.3Technology and SOI 3
Chapter 2: SOI Materials 5
2.1 Silicon on Heteroepitaxial Substrate 5
2.2 Silicon-Oxide-Silicon SOI substrates 6
2.2.1 Separation by Implantation of Oxygen 6
2.2.2 Wafer-Bonding methods for preparing SOI 8
2.2.3 SOI Materials Summary 11
2.3Comparison of SOI and Bulk 11
2.3.1 Isolation Techniques 11
2.4 SOI Technology Advantages 16
2.4.1 Capacitance Reduction 16
2.4.2 Reduced Short Channel Effect 16
2.4.3 Lower Device Threshold 16
2.4.4 Soft Error Rate (SER) Effects 17
2.5 Performance 17
2.6 Partially and Fully Depleted-SOI 18
2.7 Technology Scaling 21
2.8 SOI Device Properties 22
2.8.1 Source/Drain-to-Substrate Capacitance 22
2.8.2 Gate Leakage 22
2.9Body Effects 23
2.9.1 Bipolar Effect 23
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SOI Design: Analog, Memory & Digital Techniques
2.9.2 Kink Effect 24
2.9.3 Capacitive Body Effects 26
2.10 Body Ties 29
2.10.1 Body Tied to Substrate 31
2.10.2 Body-tied to gate Configurations 32
2.10.3 Resistive Body Tie 33
2.11 Device Noise 34
2.12 Self Heating 36
2.12.1Self Heating from elsewhere on the same chip 38
2.12.2Self Heating from within a sub-circuit 39
Chapter 3: Components 47
3.1 MOS devices 47
3.2 Diodes 49
3.3 Bipolar Transistors 49
3.4 Lateral DMOS 51
3.5 Drain Extended Devices 53
3.5.1 Design of an SOI high voltage DEMOS device. 55
3.6 Compound High Voltage SOI Structures 56
3.7 Passive Components 57
3.7.1 Resistors 57
3.7.2 Capacitors 58
3.7.3 Inductors 59
Chapter 4: SOI Modeling 63
4.1 Modeling Introduction 63
4.2 Example SOI spice deck 66
4.3 Models 68
4.3.1 BSIM 68
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SOI Design: Analog, Memory & Digital Techniques
4.4 Alternative Model Options 70
Chapter 5: Layout for SOI 75
5.1 Introduction to Layout for SOI components 75
5.2 Converting designs from Bulk to SOI 77
5.2.1 Diodes 77
5.2.2 Bipolar Transistors 79
5.3 Layout for Minimization of Thermal Self Heating Effects 80
5.3.1 Cross coupling with thermal coupling 81
5.4 Output Stages 83
Chapter 6: Static SOI Design
6.1 Introduction 85
6.1.1 Lower Fan Out Capacitance 87
6.2 Decreased Body Effect 87
6.3 Gate Leakage 88
6.4 Static Inverter Characteristics 89
6.5 Body Voltages in SOI Inverters 92
6.6 Body Voltage Convergence 94
6.6.1 Delay vs. effective gate length 94
6.7 Noise Margin In Inverters 95
6.8 Nand Gate Response 96
6.8.1 Body Voltage Response in Nand Gates 101
6.9 Nor Gate response 103
6.10 Static OR-AND SOICMOS Circuit 104
6.11 XOR Gate response in SOI 107
ix