Regular Silicon Structures aka VLSI Building Blocks

52 Pages·2009·3.36 MB·English

by  John Wawrzynek

CS250 VLSI Systems De sign
Fall 2009
John Wawrzynek, Krste Asanovic’, with John Lazzaro
Re gular Silicon St r uc t ure s
a .k . a
VLSI Building Block s
Lecture 11, Regular Structures CS250, UC Berkeley Fall ‘09
Int roduction
‣ We've experienced synthesis and standard cell place and
route.
‣ Is that all there is? We can implement any digital system
with only primitive logic gates and flip-flops.
‣ If so, chip implementations would be pretty inefficient (and
boring to do!)
‣ Key questions:
Where can special circuit- and layout-generators provide
advantage and how much?
‣ Examples with a clear advantage:
RAM blocks
‣ Example where it is not so clear:
cross-bar switches, datapaths, ROMs, multipliers
‣ We’ll start with on-chip RAM
Lecture 11, Regular Structures 2 CS250, UC Berkeley Fall ‘09
Verilog RAM Specification
//
// Single-Port RAM with Synchronous Read
//
module v_rams_07 (clk, we, a, di, do);
input clk;
input we;
input [5:0] a;
input [15:0] di;
output [15:0] do;
reg [15:0] ram [63:0];
reg [5:0] read_a;
always @(posedge clk) begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule
What do the synthesis tools do with this?
Lecture 11, Regular Structures 3 CS250, UC Berkeley Fall ‘09
Memor y-Block Basics
log (M)
2
M X N memory:
Depth = M, Width = N.
M words of memory, each word N bits wide.
VLSI tools flows include parameterized RAM-generators. User
specifies width, depth, (sometimes) aspect ratio; gets simulation &
timing models, layout.
Lecture 11, Regular Structures 4 CS250, UC Berkeley Fall ‘09
Internal Memor y Organization
2-D arrary of bit
cells. Each cell
stores one bit of
data.
Special circuit tricks are
used for the cell array to
improve storage density.
‣ RAM/ROM naming convention:
‣ examples: 32 X 8, "32 by 8" => 32 8-bit words
‣ 1M X 1, "1 meg by 1" => 1M 1-bit words
Lecture 11, Regular Structures 5 CS250, UC Berkeley Fall ‘09
Addre ss Decoding
sel_row1
address sel_row0
Address
• The function of the address decoder is
to generate a one-hot code word from
the address.
• The output is use for row selection.
• Many different circuits exist for this
function. A simple one is shown to the
right.
Lecture 11, Regular Structures 6 CS250, UC Berkeley Fall ‘09
Memor y Block Internals
sel_row0
For read operation,
functionally the memory is
equivalent to a 2-D array sel_row1
off flip-flops with tristate
outputs on each:
For write operation, functionally equivalent
includes a means to change state value: These circuits are just
functional abstractions of the
actual circuits used.
Lecture 11, Regular Structures 7 CS250, UC Berkeley Fall ‘09
Storing computational state as charge
State is coded as the
+++ +++
amount of energy stored
by a capacitor.
--- ---
1.5V
State is read by
+++ +++
sensing the amount
--- --- of energy
Problems: noise changes Q (up or down),
parasitics leak or source Q. Fortunately,
8
Q cannot change instantaneously, but that only
gets us in the ballpark.
Lecture 11, Regular Structures CS250, UC Berkeley Fall ‘09
Static Memor y Circuits
Dynamic Memory: Circuit remembers
for a fraction of a second.
Static Memory: Circuit remembers as
long as the power is on.
Non-volatile Memory: Circuit remembers
for many years, even if power is off.
9
Lecture 11, Regular Structures CS250, UC Berkeley Fall ‘09
Ide a: Store e ach bit with its
complement
x x
“Row”
Why?
Gnd Vdd
Vdd Gnd
y y
We can use the redundant
representation to compensate
for noise and leakage.
10
Lecture 11, Regular Structures CS250, UC Berkeley Fall ‘09