Low-Power Audio Codec With Audio Processing and Stereo Class-D Speaker Amplifier

132 Pages·2016·1.96 MB·English

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TLV320AIC3110
SLAS647C–DECEMBER2009–REVISEDMAY2016
TLV320AIC3110 Low-Power Audio Codec With Audio Processing
and Stereo Class-D Speaker Amplifier
1 Device Overview
1.1 Features
1
• StereoAudioDACWith95-dBSNR Volume-ControlSettings
• MonoAudioADCWith91-dB SNR • DigitalSine-WaveGeneratorfor BeepsandKey-
Clicks
• Supports8-kHzto192-kHzSeparateDACand
ADCSampleRates • IntegratedPLLUsedfor ProgrammableDigital
AudioProcessor
• Stereo1.29-WClass-D BTL8-Ω SpeakerDriver
WithDirect BatteryConnection • I2S,Left-Justified,Right-Justified,DSP,and TDM
AudioInterfaces
• OneDifferentialandThreeSingle-EndedInputs
WithMixingandLevelControls • I2CControlWithRegister Auto-Increment
• MicrophoneWithBias,PreampPGA,andAGC • FullPower-Down Control
• Built-inDigital AudioProcessingBlocks(PRB)With • PowerSupplies:
User-ProgrammableBiquad,FIRFilters,andDRC – Analog:2.7V–3.6V
• DigitalMixingCapability – DigitalCore:1.65V–1.95V
• ProgrammableDigital AudioProcessorforBass – DigitalI/O:1.1V–3.6V
Boost/Treble/EQWithuptoFiveBiquadsfor – Class-D:2.7V–5.5V(SPLVDDandSPRVDD ≥
RecordanduptoSixBiquadsforPlayback AVDD)
• PinControlorRegisterControlforDigital-Playback • 5-mm×5-mm 32-VQFNPackage
1.2 Applications
• PortableAudioDevices • e-Books
• MobileInternetDevices
1.3 Description
The TLV320AIC3110 device is a low-power, highly integrated, high-performance codec that supports
stereoaudioDAC,andmonoaudioADC.
The TLV320AIC3110 device features a high-performance audio codec with 24-bit stereo playback and
monaural record functionality. The device integrates several analog features, such as a microphone
interface, headphone drivers, and speaker drivers. The digital-audio data format is programmable to work
withpopularaudiostandardprotocols(I2S,left-justifiedandright-justified)inmaster,slave,DSP,andTDM
modes. Bass boost, treble, or EQ is supported by the programmable digital-signal processing blocks
(PRB). An on-chip PLL provides the high-speed clock required by the digital-signal processing block. The
volume level is controlled either by pin control or by register control. The audio functions are controlled
usingtheI2Cserial bus.
The TLV320AIC3110 device has a programmable digital sine-wave generator and is available in a 32-pin
VQFNpackage.
DeviceInformation(1)
PARTNUMBER PACKAGE BODYSIZE(NOM)
TLV320AIC3110 VQFN(32) 5.00mm×5.00mm
(1) Forallavailablepackages,seetheorderableaddendumattheendofthedatasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TLV320AIC3110
SLAS647C–DECEMBER2009–REVISEDMAY2016 www.ti.com
1.4 Functional Block Diagram
SPLVDD SPRVDD SPLVSS SPRVSS HPVDD HPVSS AVDD AVSS
MICBIAS 2 V/2.5 V/AVDD P1/R33–R34 De-Pop
and Audio Output Stage
VOL/ Soft- Power Management
MICDET 7-BitADC P0/R116 Start
Left and Right Volume-
Control Register RC CLK
P0/R116
Class-D Speaker AnalogAttenuation
Driver 0 dB to–78 dB and Mute GPIO GPIO1
(0.5-dB Steps / Nonlinear)
SPLP P1/R42 P1/R38 MIX_L
SPLM
6 dB to 24 dB (6-dB Steps)
SPRP P1/R32 P1/R43 P1/R39 MIX_R I2C SSCDLA
SPRM
P1/R30
ClassA/B AnalogAttenuation
Headphone/Lineout 0 dB to–78 dB and Mute
Driver (0.5-dB Steps / Nonlinear)
P1/R40 P1/R36 MIX_L
HPL
P1/R31 0 dB to 9 dB (1-dB Steps) Note: Normally,
MCLK is PLLinput;
P1/R44 P1/R41 P1/R37 MIX_R however, BCLK,
HPR GPIO1, etc., can
also be PLLinput.
MIX_R
MIX_L PLL MCLK
MIC1LP
S DAC_L D-S S S
DAC
MIC1RP Digital Vol
P1/R35 24 dB to Processing P0/R63
Mute Blocks Digital
Audio
S DAC_R D-S S S Processing
DAC P0/ PRB_P1– and
R64–R65 PRB_P25 Serial
Digital P0/R71 Digital Beep Interface DOUT
P0/R72
Vol Ctl Generator WCLK
0 to–63 dB
(1-dB Steps) DIN
P1/R47
0 to 59.5 dB BCLK
MIC1LP (0.5-dB steps) MonoADC P0/R82–R83 Processing
S D-S Digital Vol Blocks
ADC –12..20 dB RESET
MIC1RP Step = 0.5 dB PRB_R4–
P1/R48 PRB_R18
Selectable P0/R86–R93
Gain/Input
Impedance AGC
S
MIC1LM
OSC
VCOM
Input CM Selectable P1/R49 RC CLK
P1/R50 Gain/Input
Impedance
DVDD DVSS IOVDD IOVSS
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Table of Contents
1 DeviceOverview......................................... 1 6 ParameterMeasurementInformation.............. 18
1.1 Features.............................................. 1 7 DetailedDescription................................... 19
........................................... ............................................
1.2 Applications 1 7.1 Overview 19
............................................ ...........................
1.3 Description 1 7.2 FunctionalBlockDiagram 20
............................ .................................
1.4 FunctionalBlockDiagram 2 7.3 FeatureDescription 20
2 Revision History......................................... 3 7.4 RegisterMap........................................ 80
3 Device Comparison..................................... 5 8 ApplicationandImplementation................... 120
4 PinConfigurationandFunctions..................... 6 8.1 ApplicationInformation............................ 120
......................................... .................................
4.1 PinAttributes 6 8.2 TypicalApplication 120
5 Specifications ............................................ 8 9 PowerSupplyRecommendations................. 123
5.1 AbsoluteMaximumRatings.......................... 8 10 Layout................................................... 124
.......................................... ..................................
5.2 ESDRatings 8 10.1 Layout Guidelines 124
................ ....................................
5.3 RecommendedOperatingConditions 8 10.2 Layout Example 124
5.4 Thermal Information.................................. 9 11 DeviceandDocumentationSupport.............. 125
............................. .............................
5.5 ElectricalCharacteristics 9 11.1 CommunityResources 125
.......................... ........................................
5.6 PowerDissipationRatings 10 11.2 Trademarks 125
5.7 I2S,LJF,andRJFTiminginMasterMode.......... 11 11.3 ElectrostaticDischargeCaution................... 125
5.8 I2S,LJF,andRJFTiminginSlaveMode........... 11 11.4 Glossary............................................ 125
5.9 DSPTiminginMasterMode........................ 11 12 MechanicalPackagingandOrderable
......................... Information............................................. 125
5.10 DSPTiminginSlaveMode 11
5.11 I2CInterfaceTiming................................. 12 12.1 PackagingInformation............................. 125
..............................
5.12 TypicalCharacteristics 15
2 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionB(May2012)toRevisionC Page
• AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,Applicationand
Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation
Supportsection,andMechanical,Packaging,andOrderableInformationsection........................................... 1
• AddedPower-SupplySequencesectiontotheDeviceInitializationsection................................................ 20
• AddedthereferencetothePGAGainVersusInputImpedancetableintheMICBIASandMicrophone
Preamplifiersection................................................................................................................. 27
• ChangedunitsinTable7-15fromktokΩ....................................................................................... 27
• ChangedSDINterminaltoDINinFigure7-16.................................................................................. 40
• ChangedSection7.3.10.1.2diagramsforPRB_P2/5/8/10/13/15/18/21/24/25toreflectthattheDRC_HPFfilter
cannotbebypassedwhentheDRCisturnedoff .............................................................................. 43
• Addedsequenceforinsertingabeepinthemiddleofanalready-playingsignalandnotetextfollowingscriptin
theKey-ClickFunctionalityWithDigitalSine-WaveGenerator(PRB_P25)section........................................ 59
• AddednotetoRegisterMapsection.............................................................................................. 80
• ChangedDOSRnoteinPage0/Register14byswitchingmultiplevalueforFilterTypeAandFilterTypeC........ 83
• AddedADCOSRnotetoPage0/Register20................................................................................. 84
• ChangedvaluesinPage0/Register69(0x45):DRCControl2............................................................. 95
• ChangedPage0,Register70,bitD3-D0decayratevaluefor0000fromDR=1.5625e–3toDR=0.015625........ 95
• SwitchedD1andD0descriptionssothatD1isforSPandD0isforHPinPage1/Register30table............... 103
• ChangedPage1/Register40,D1toreserved............................................................................... 106
• ChangedPage1/Register41,D1toreserved............................................................................... 106
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ChangesfromRevisionA(April2012)toRevisionB Page
• ChangedfootnoteinD7=1table;addedD6–D0totheRegisterValuecolumns,andchangedAnalogAttenuation
toAnalogGain....................................................................................................................... 62
• UpdatedAOSRvaluesinClockDistributionTreeimage ..................................................................... 66
• DeletedextracharacterfromtitleofPage0/Register75..................................................................... 96
• ChangedDescriptionvalueinPage0/Register83forbitsD6–D0.......................................................... 97
• Removedextracross-referencefromPage1/Register36–39............................................................. 105
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3 Device Comparison
Table3-1.DeviceFeaturesComparison
FUNCTION TLV320AIC3100 TLV320AIC3110 TLV320AIC3111 TLV320AIC3120
DACs 2 2 2 1
ADCs 1 1 1 1
Inputs/Outputs 3/3 3/4 3/4 3/2
Resolution(Bits) 16,20,24,32 16,20,24,32 16,20,24,32 16,20,24,32
ControlInterface I2C I2C I2C I2C
DigitalAudioInterface LJ,RJ,I2S,TDM,DSP LJ,RJ,I2S,TDM,DSP LJ,RJ,I2S,TDM,DSP LJ,RJ,I2S,TDM,DSP
NumberofDigitalAudioInterfaces 1 1 1 1
SpeakerAmplifierType MonoDifferential StereoDifferential StereoDifferential MonoDifferential
Class-D Class-D Class-D Class-D
ConfigurableminiDSP No No Yes Yes
HeadphoneDriver Yes Yes Yes Yes
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4 Pin Configuration and Functions
RHB Package
(Top View)
D D S
VD M P VD VS M S D
R R L L L L S D
P P P P P P V V
S S S S S S D A
24 23 22 21 20 19 18 17
SPRVSS 25 16 AVSS
SPRP 26 15 MIC1LM
HPL 27 14 MIC1RP
HPVDD 28 13 MIC1LP
HPVSS 29 12 MICBIAS
HPR 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
S D D T N K K K
VS VD VD OU DI CL CL CL
O O D D W B M
I I
P0048-09
4.1 Pin Attributes
Table4-1.PinFunctions
PIN
I/O DESCRIPTION
NAME NO.
AVDD 17 - Analogpowersupply
AVSS 16 - Analogground
BCLK 7 I/O Audioserialbitclock
DOUT 4 O Audioserialdataoutput
DVDD 3 - Digitalpower–digitalcore
DVSS 18 - Digitalground
GPIO1 32 I/O General-purposeinput/outputpinandmultifunctionpin
HPL 27 O Left-channelheadphoneandlinedriveroutput
HPR 30 O Right-channelheadphoneandlinedriveroutput
HPVDD 28 - HeadphoneandlinedriverandPLLpower
HPVSS 29 - HeadphoneandlinedriverandPLLground
IOVDD 2 - Interfacepower
IOVSS 1 - Interfaceground
MCLK 8 I Externalmasterclock
MICBIAS 12 O Microphonebiasvoltage
MIC1LM 15 I MicrophoneandlineinputroutedtoMorPinputmixer
MIC1LP 13 I MicrophoneandlineinputroutedtoPinputmixerandleftoutputmixer
MIC1RP 14 I MicrophoneandlineinputroutedtoPinputmixerandleftandrightoutputmixer
RESET 31 I Devicereset
SCL 10 I/O I2Ccontrolbusclockinput
SDA 9 I/O I2Ccontrol-busdatainput
SPLM 19 O Left-channelclass-Dspeakerdriverinvertingoutput
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Table4-1. PinFunctions (continued)
PIN
I/O DESCRIPTION
NAME NO.
SPLP 22 O Left-channelclass-Dspeakerdrivernoninvertingoutput
SPLVDD 21 - Left-channelclass-Dspeakerdriverpowersupply
SPLVSS 20 - Left-channelclass-Dspeaker-amplifierpower-supplyground
SPRM 23 O Right-channelclass-Dspeakerdriverinvertingoutput
SPRP 26 O Right-channelclass-Dspeakerdrivernoninvertingoutput
SPRVDD 24 - Right-channelclass-Dspeakerdriverpowersupply
SPRVSS 25 - Right-channelclass-Dspeakerdriverpowersupplyground
VOL/MICDET 11 I Volumecontrolormicrophonedetection
WCLK 6 I/O Audioserialwordclock
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5 Specifications
5.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
MIN MAX UNIT
AVDDtoAVSS –0.3 3.9 V
DVDDtoDVSS –0.3 2.5 V
HPVDDtoHPVSS –0.3 3.9 V
SPLVDDtoSPLVSS –0.3 6 V
SPRVDDtoSPRVSS –0.3 6 V
IOVDDtoIOVSS –0.3 3.9 V
Digitalinputvoltage IOVSS–0.3 IOVDD+0.3 V
Analoginputvoltage AVSS–0.3 AVDD+0.3 V
Operatingtemperature –40 85 °C
Junctiontemperature(T Max) 105 °C
J
Storagetemperature,T –55 150 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
5.2 ESD Ratings
VALUE UNIT
Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2500
V V
(ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
5.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS (2) 1.65 1.8 1.95
HPVDD ReferencedtoHPVSS(2) 2.7 3.3 3.6
Power-supplyvoltagerange V
SPLVDD(1) ReferencedtoSPLVSS(2) 2.7 5.5
SPRVDD(1) ReferencedtoSPRVSS(2) 2.7 5.5
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
Resistanceappliedacrossclass-D
Speakerimpedance 8 Ω
ouputpins(BTL)
Headphoneimpedance ACcoupledtoR 16 Ω
L
V Analogaudiofull-scaleinputvoltage AVDD=3.3V,single-ended 0.707 V
I RMS
Stereo-lineoutputloadimpedance ACcoupledtoR 10 kΩ
L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
SCL SCLclockfrequency 400 kHz
T Operatingfree-airtemperature –40 85 °C
A
(1) Tominimizebattery-currentleakage,theSPLVDDandSPRVDDvoltagelevelsmustnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheymustnotdifferinvoltagebymorethan0.2-Vmaximumforanycombinationofground
signals.Ensurealow-impedanceconnectionbetweenHPVSSandDVSSthroughtheuseofawidetraceorgroundplane,.
(3) Themaximuminputfrequencymustbe50MHzforanydigitalpinusedasageneral-purposeclock.
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5.4 Thermal Information
TLV320AIC3110
THERMALMETRIC(1) RHB(VQFN) UNIT
32PINS
R Junction-to-ambientthermalresistance 32.7 °C/W
θJA
R Junction-to-case(top)thermalresistance 23.3 °C/W
θJC(top)
R Junction-to-boardthermalresistance 6.6 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 0.3 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 6.5 °C/W
JB
R Junction-to-case(bottom)thermalresistance 2.0 °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report,SPRA953.
5.5 Electrical Characteristics
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD=SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALOSCILLATOR-RC_CLK
OscillatorfrequencyforSAR 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETpinenabled
VOL/MICDETpinconfiguredasvolumecontrol(page0/register116,bitD7=1and 0.5×
Inputvoltagerange 0 V
page0/register67,bitD7=0) AVDD
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
AUDIOADC
MicrophoneInputtoADC,984-HzSine-WaveInput,fS=48kHz,AGC=OFF
Inputsignallevel(0-dB) MICwithR1=20kΩ(page1/register48andregister49,bitsD7-D6) 0.707 VRMS
SNR Signal-to-noiseratio fcSh=an4n8elkHnozi,s0e-,dAB-wPeGigAhtgeadin(1,)M(2)ICinputAC-shortedtoground;measuredasidle- 80 91 dB
Dynamicrange ftSo=0.47807k-HVzR,M0S-idnBpuPt,GAA-wgeaiignh,tMedIC(1)in(2p)ut1kHzat–60-dBFSinputapplied,referenced 91 dB
THD+N Totalharmonicdistortion+noise fS=48kHz,0-dBPGAgain,MICinput1kHzat–2dBFSinputapplied,referencedto –85 –70 dB
0.707-VRMSinput
THD Totalharmonicdistortion fS=48kHz,0-dBPGAgain,MICinput1kHzat–2dBFSinputapplied,referencedto –91 dB
0.707-VRMSinput
Inputcapacitance MICinput 2 pF
MicrophoneBias
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,bitsD1–D0=10(MICBIAS=2.5V) 5
Voltageregulation mV
At4-mAloadcurrent,page1/register46,bitsD1–D0=01(MICBIAS=2V) 7
AudioADCDigitalDecimationFilterCharacteristics
SeeSection7.3.9.4.4foraudioADCdecimationfiltercharacteristics.
AUDIODAC
DACHEADPHONEOUTPUT,AC-coupledload=16Ω(single-ended),drivergain=0dB,parasiticcapacitance=30pF
Full-scaleoutputvoltage(0dB) Outputcommon-modesetting=1.65V 0.707 VRMS
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1)(2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
THD+N Totalharmonicdistortion+noise 0-dBFSinput –82 –60 dB
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB
PO Maximumoutputpower RRLL==3126ΩΩ,,TTHHDD++NN==––6600ddBB 2600 mW
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
HPL HPVDD
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Electrical Characteristics (continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD=SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACLINEOUT(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
THD+N Totalharmonicdistortion+noise 0-dBFSinput,0-dBgain –83 dB
DACDigitalInterpolationFilterCharacteristics
SeeSection7.3.10.1.4forDACinterpolationfiltercharacteristics.
DACOUTPUTtoCLASS-DSPEAKEROUTPUT;Load=8Ω(differential),50pF
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DACinput=0dBFS,DACCM
2.2
(page1/register31,bitsD4–D3)=1.65V,class-Dgain=6dB,THD=–16.5dB
Outputvoltage SPLVDD=SPRVDD=3.6V,BTLmeasurement,DACinput=–2dBFS,DACCM VRMS
2.1
(page1/register31,bitsD4–D3)=1.65V,class-Dgain=6dB,THD=–20dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DACinput=mute,class-Dgain=6
Output,common-mode 1.8 V
dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,class-Dgain=6dB,measuredas
SNR Signal-to-noiseratio idle-channelnoise,A-weighted(withrespecttofull-scaleoutputvalueof2.2VRMS)(1) 87 dB
(2)
SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,DACinput=–6dBFS,
THD Totalharmonicdistortion –67 dB
class-Dgain=6dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,DACinput=–6dBFS,
THD+N Totalharmonicdistortion+noise –66 dB
class-Dgain=6dB
PSRR Power-supplyrejectionratio(4) SPLVDD=SPRVDD=3.6V,BTLmeasurement,rippleonSPLVDD/SPRVDD=200 –44 dB
mVp-pat1kHz
Muteattenuation 110 dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
540 mW
THD=10%
SPLVDD=SPRVDD=4.3V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
PO Maximumoutputpower THD=10% 790 mW
SPLVDD=SPRVDD=5.5V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
1.29 W
THD=10%
Output-stageleakagecurrentfordirect
SPLVDD=SPRVDD=4.3V,deviceispowereddown(power-up-resetcondition) 80 nA
batteryconnection
ADCandDACPOWERCONSUMPTION
ForADCandDACpowerconsumptionbasedperselectedprocessingblock,seeSection7.3.8.
DIGITALINPUT/OUTPUT
Logicfamily CMOS
0.7×
VIH IIH=5µA,IOVDD=1.6V IOVDD
IIH=5µA,IOVDD=1.6V IOVDD
0.3×
VIL LogicLevel IIL=5µA,IOVDD=1.6V –0.3 IOVDD V
IIL=5µA,IOVDD=1.6V 0
0.8×
VOH IOH=2TTLloads IOVDD
0.1×
VOL IOL=2TTLloads IOVDD
Capacitiveload 10 pF
(4) DACtospeaker-outPSRRisadifferentialmeasurementcalculatedasPSRR=20×log(ΔV /ΔV ).
SPL(P+M) SPLVDD
5.6 Power Dissipation Ratings
Thisdatawastakenusing2-oz.(0,071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer
3-inch×3-inch(7,62-cm×7,62-cm)PCB.
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
2.3W 28.57mW/°C 1W 0.6W
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