Information processing apparatus, information processing method, and computer program product ...

44 Pages·2013·2.78 MB·English

US008275730B2
(12) United States Patent (10) Patent No.: US 8,275,730 B2
Nagao (45) Date of Patent: Sep. 25, 2012
(54) INFORMATION PROCESSING APPARATUS, OTHER PUBLICATIONS
INFORMATION PROCESSING METHOD,
John E. Hopcroft et al., “Equivalence and Minimization of
AND COMPUTER PROGRAM PRODUCT FOR Automata”. Introduction to Automata Theory, Languages, and Com
REDUCING STATES IN A DETERMINISTIC putation, Second Edition, Chapter 4, Section 4, 2000, pp. 154-165.
FINITE STATE AUTOMATON AlfredV. Aho et al., “Optimization of DFA-Based Pattern Matchers”,
Compilers Principles, Techniques, and Tools, Chapter 3, Section 9,
(75) Inventor: Manabu Nagao, Tokyo (JP) 1985, ISBN 0-201-10088-6, pp. 141-144.
John Hopcroft, “An n Log n Algorithm for Minimizing States in a
Finite Automaton”, Theory of Machines and Computations,
(73) Assignee: Kabushiki Kaisha Toshiba, Tokyo (JP)
Acadamic Press, NeWYork, 1971, pp. 189-196.
Bruce W. Watson, “An Incremental DFA Minimization Algorithm”,
( * ) Notice: Subject to any disclaimer, the term of this Proceedings Second International Workshop on Finite State Methods
patent is extended or adjusted under 35 in Natural Language Processing (FSMNLP 2001), Jun. 4, 2001, 9
U.S.C. 154(b) by 484 days. pages.
Bruce W. Watson et al., “An Ef?cient Incremental DFA Minimization
(21) Appl.No.: 12/558,761 Algorithm”, Natural Language Engineering 9(1), 2003, pp. 49-64.
* cited by examiner
(22) Filed: Sep. 14, 2009
Primary Examiner * Alan Chen
(65) Prior Publication Data (74) Attorney, Agent, or Firm * Oblon, Spivak,
US 2010/0082522 A1 Apr. 1, 2010 McClelland, Maier & Neustadt, L.L.P.
(30) Foreign Application Priority Data (57) ABSTRACT
States included in a deterministic ?nite automaton are classi
Sep. 26, 2008 (JP) ............................... .. 2008-249029 ?ed into states having the same input symbols associated With
outgoing transitions and the same ?nality, and a calculates an
(51) Int. Cl.
intersection set between each of the state sets and a set of
G06F 17/00 (2006.01) transition destination states Which is obtained by translating
G06F 7/60 (2006.01)
each of states included in the state sets, until the number of
G06F 7/38 (2006.01)
states included in the intersection set becomes equal to one,
(52) US. Cl. ............................... .. 706/45; 703/2; 326/46 While regarding the set of the transition destination states for
(58) Field of Classi?cation Search ...................... .. None each of the input symbol included in the intersection set as
See application ?le for complete search history. neW state sets, and plural indistinguishable states are merged
into one state by tracing a route in a reverse direction to a
(56) References Cited transition direction, When the number of states has become
equal to one.
U.S. PATENT DOCUMENTS
2007/0130140 A1* 6/2007 Cytron et al. ................... .. 707/6 10 Claims, 23 Drawing Sheets
(10
STATE-NUMBER REDUCING UNIT
(11
STATE CLASSIFYING UNIT
(12
CALCULATING UNIT
STATE MERGING UNIT ’\_/ 121
TRANSITION-DESTINATION- /-\
/122
SET GENERATING UNIT
INDISTINGUISHABLE-SET /
GENERATING UNIT \J123
INDISTINGUISHABLE
CANDIDATE-SET /\J 124
GENERATING UNIT
\ /
US. Patent Sep. 25, 2012 Sheet 1 0f 23 US 8,275,730 B2
0 s2 33
CPU OPERATING DISPLAY
UNIT UNIT
A A
v v S7
A A k
S4 v S5 v 86
STORAGE
ROM RAM UNIT
S10
STATE-NUMBER REDUCING UNIT
811
STATE CLASSIFYING UNIT
S12
CALCULATING UNIT
STATE MERGING UNIT /\J 121
TRANSITION-DESTINATION
SET GENERATING UNIT
INDISTINGUISHABLE-SET /
GENERATING UNIT \J123
INDISTINGUISHABLE
CANDIDATE-SET /\/ 124
GENERATING UNIT
US. Patent Sep. 25, 2012 Sheet 2 0f 23 US 8,275,730 B2
FIG.3
CLASSIFY INTO STATES EACH HAVING SAME SET OF FINALITY
AND INPUT SYMBOL OF OUTGOING TRANSITION 101
TO GENERATE SET G OF CLASSES
gN102
YES
IS G EMPTY SET Q5 ?
NO
SELECT ONE STATE SET INCLUDED IN G AND EXECUTE
"search_equiv" FOR SELECTED STATE SET 9 N103
search_equiv
" N110
GENERATE SET Z 9 OF INPUT SYMBOLS OF OUTGOING
TRANSITIONS FROM 9 N111
LOOP 1
END CONDITION: ALL PROCESSES FOR INPUT SYMBOLS
N112
INCLUDED IN 29 ARE COMPLETED
DERIVE SET gr1 OF TRANSITION DESTINATION STATES OF 9 ON
SELECTED INPUT SYMBOL N113
OBTAIN INTERSECTION SET OF gr1 AND EACH ELEMENT IN G
AND RECURSIVELY EXECUTE "search_equiv" BY ASSUMING
N114
INTERSECTION SET AS 9 WHEN INTERSECTION SET SIZE IS
EQUAL TO OR LARGER THAN 2
||f||||lI|I||I||||||||||||lllII|||l||||||l|||IIvI||||||||aI|II||II||II| |||||||||||||II|I|||| |
LOOP 1 N115
MERGE INDISTINGUISHABLE STATES AMONG g
INTO ONE STATE, RESPECTIVELY
WHEN THERE ARE STATES DEPENDING ON STATES TO BE N116
MERGED, MERGE SUCH STATES INTO ONE, RESPECTIVELY
DETERMINE WHETHER 9 IS ON CYCLIC PATH AND RECORD
INFORMATION OF DEPENDENCE DESTINATION WHEN 9 IS N117
ON CYCLIC PATH
WHEN 9 IS NOT ON CYCLIC PATH, REMOVE 9 FROM G
N118
REMOVE STATES ERASED BY MERGE FROM G
N119

US. Patent Sep. 25, 2012 Sheet 8 0f 23 US 8,275,730 B2
US. Patent
Sep. 25, 2012 Sheet 9 0f 23 US 8,275,730 B2
F|G.13
(
STACK S
{(1, 1), (2, 2), (3, 3), (4, 4)}
, _ _ _ _ _ . _ _ _
_ _ _ _ _ _ _ _ _ _/