Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)

245 Pages·2013·8.58 MB·English

by  Sridhar Gangadharan

Sridhar Gangadharan · Sanjay Churiwala
Constraining
Designs for
Synthesis and
Timing Analysis
A Practical Guide to Synopsys Design
Constraints (SDC)
Constraining Designs for Synthesis
and Timing Analysis

Sridhar Gangadharan Sanjay Churiwala
●
Constraining Designs
for Synthesis and Timing
Analysis
A Practical Guide to Synopsys Design
Constraints (SDC)
with Chapter 17 contributed by
Frederic Revenu
Sridhar Gangadharan Sanjay Churiwala
Atrenta, Inc. Xilinx
San Jose , CA , USA Hyderabad, India
ISBN 978-1-4614-3268-5 ISBN 978-1-4614-3269-2 (eBook)
DOI 10.1007/978-1-4614-3269-2
Springer New York Heidelberg Dordrecht London
Library of Congress Control Number: 2013932651
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Foreword
It has been said that “timing is everything.” While that is certainly true if you’re in
show business, the same holds true if you’re designing a system-on-a-chip (SoC).
SoCs are powering the hand-held consumer electronics revolution going on all
around us. They make things like smart phones and tablets possible. Correct defi ni-
tion and management of timing constraints for an SoC are critical tasks. How well
these tasks are done will impact the success of the chip project.
An SoC is typically a collection of many complex building blocks sourced from
multiple suppliers. It is the designer’s job to stitch all these blocks together and
achieve the sometimes competing goals of power, performance, and cost for the
chip. And all of this happens while the whole team is under tremendous schedule
pressure. The fact that so many SoC devices work the fi rst time is nothing short of
a miracle. There are many challenges associated with SoC design and many signifi -
cant technologies that help make them possible.
In the chapters that follow, Sridhar Gangadharan and Sanjay Churiwala take an in-
depth look at timing constraints. The broad impact that timing constraints have on the
success of an SoC design project is discussed. Many examples are presented for both
ASIC and FPGA design paradigms. On the surface, defi ning timing constraints appears
to be a straightforward process. It is, in fact, a complex process with many important
nuances and interrelationships. Sridhar and Sanjay do an excellent job explaining the
process with many relevant examples and detailed “how to” explanations.
As designs have grown in complexity, much effort has gone into initiatives focused
on improving design effi ciency and managing risk. What is not fully understood is
the impact that timing constraints have on both. Poorly managed or incorrect
constraints can have signifi cant negative impact on design effort and can lead to a
chip failure. The chances of this occurring are growing with every new technology
v
vi Foreword
node. I believe that timing constraints are coming upon us as a major area of design
challenge, and I congratulate Sridhar and Sanjay for developing such a complete
guide for this important topic. I hope you fi nd it useful as well.
Dr. Ajoy Bose
Chairman, President and CEO, Atrenta Inc.
San Jose, CA, USA
Preface
Dear Friends,
In today’s world of deep submicron, Timing has become a critical challenge for
designers developing Application Specifi c Integrated Circuits (ASIC ) or System on
a chip (SoC). Design engineers spend many cycles iterating between different stages
of the design fl ow to meet the timing requirements. Timing is not merely a response
time of a chip, but an integral part of the chip functionality that ensures that it can
communicate with other components on a system seamlessly. That begs the ques-
tion, what is timing? How do you specify it?
This book serves as a hands-on guide to writing and understanding timing con-
straints in integrated circuit design. Readers will learn to write their constraints
effectively and correctly, in order to achieve the desired performance of their IC or
FPGA designs, including considerations around reuse of the constraints. Coverage
includes key aspects of the design fl ow impacted by timing constraints, including
synthesis, static timing analysis, and placement and routing. Concepts needed for
specifying timing requirements are explained in detail and then applied to specifi c
stages in the design fl ow, all within the context of Synopsys Design Constraints
(SDC), the industry-leading format for specifying constraints.
We have often heard from many design engineers that there are several books explain-
ing concepts like Synthesis and Static Timing Analysis which do cover timing constraints,
but never in detail. This book is our attempt at explaining the concepts needed for specify-
ing timing requirements based on many years of work in the areas of timing characteriza-
tion, delay calculation, timing analysis, and constraints creation and verifi cation.
Book Organization
Here’s how the book is laid out:
Chapters 1 , 2 , and 3 introduce the subject of Timing Analysis – including its need
in the context of design cycle. The descriptions in these chapters are vendor, language,
and format-independent.
vii
viii Preface
Chapter 4 provides an overview of the Tcl language, because SDC (Synopsys
Design Constraints) acts as an extension to Tcl. The concept of SDC is also intro-
duced in this chapter.
These fi rst four chapters might be thought of as Introduction section.
Chapters 5 through 8 together form a section which talks about clocks, explaining
how to apply clock-related constraints. These chapters explain various kinds of
clocks and their relationships and how to specify those in SDC.
Chapters 9 and 1 0 explain how to apply constraints on the remaining (non-clock)
ports. With this section, all the primary ports are covered.
Chapters 1 1 , 12 , and 13 explain the need for timing exceptions. These chapters then
go on to explain how to specify the exceptions correctly in SDC.
Chapters 1 4 and 15 deal with much more specialized topics. These concepts are
less about individual constraints. Rather they delve into how design teams
manage the world of constraints as they move across the fl ow, from front-end
to back-end, partitioning the complete design to blocks and when integrating
individual blocks.
In Chap. 1 6 , we explain some other commands of SDC, which might have an impact
on Timing Analysis.
Some of the commands are still not covered in this book. However, with the
fundamental understanding gained on Timing Analysis and SDC through these
chapters, it should be possible for a user to easily comprehend any remaining com-
mands, including any extensions that might come in future versions of SDC.
Most tools which support SDC typically also allow some extensions to SDC in
order to achieve higher accuracy or better ease of use for the specifi c tool. Chapter 1 7
provides an overview of the Xilinx extensions to the SDC timing constraints – for
their product Vivado™.
Conventions Used in This Book
In general, the names of SDC keywords and its options are printed in i talics . Italics
are also used to represent words that have a special meaning as it relates to this book.
Additional Resources
SDC is an open source format distributed by Synopsys, Inc. SDC Documentation
and parsers can be downloaded for free from Synopsys website.
Preface ix
Feedback
We have put in our best efforts to provide an accurate description of the concepts.
We also got help from some experts in the industry to review the material for
accuracy. However, if you fi nd some descriptions confusing or erroneous, please let
us know.
Happy Reading!
Sanjay Churiwala
Sridhar Gangadharan