BiCMOS Technology and Applications

411 Pages·1993·17.91 MB·English

by  A. R. Alvarez (auth.), A. R. Alvarez (eds.)

BiCMOS Technology
and
Applications
Second Edition
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
Other books in the series:
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VHDL '92, THE NEW FEATURES OF THE VHDL HARDWARE DESCRIPTION
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APPLICATION DRIVEN SYNTHESIS, F. Catthoor, L. Svensson
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ALGORITHMS FOR SYNTHESIS AND TESTING OFASYNCHRONOUS CIRCUITS, L.
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HOT-CARRIER RELIABILITY OF MOS nSI CIRCUITS, Y. Leblebici, S. Kang
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MOTION ANALYSIS AND IMAGE SEQUENCE PROCESSING, M. I. Sezan, R. Lagendijk
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SIGMA DELTA MODULATORS: Nonlinear Decoding Algorithms and Stability Analysis, S.
Hein, A. Zakhor
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THE SECD MICROPROCESSOR, A VERIFICATION CASE STUDY, B. T. Graham
BiCMOS Technology
and
Applications
Second Edition
edited by
A. R. Alvarez
Cypress Semiconductor Corporation
~.
Springer Science+Business Media, LLC
"
Library of Congress Cataloging-in-Publication Data
BiCMOS technology and applications / edited by AR. Alvarez. -- 2nd
ed.
p. cm. -- (The Kluwer international se ries in engineering and
computer science ; SECS 244. VLSl, computer architecture and digital
signal processing)
lncludes bibliographical references and index.
ISBN 978-1-4613-6413-9 ISBN 978-1-4615-3218-7 (eBook)
DOI 10.1007/978-1-4615-3218-7
1. Metal oxide semiconductors, Complementary. 2. Bipolar
integrated circuits. I. Alvarez, AR. (Antonio R.) II. Series:
Kluwer international series in engineering and computer science
SECS 244. III. Series: Kluwer international series in engineering
and computer science. VLSl, computer architecture, and digital
signal processing.
TK7871.99.M44B53 1993
621.39'732--dc20 93-14295
ClP
Copyright © 1993 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1993
Softcover reprint of the hardcover 2nd edition 1993
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher,
Springer Science+Business Media, LLC.
Printed on acid-free paper.
Dedication
This book is dedicated in Memory of Roger Haken.
Contents
Preface xv
Chapter 1. Introduction to BiCMOS
A.R. Alvarez (Cypress Semiconductor Corp.)
1.0 Introduction 1
1.1 BiCMOS Historical Perspective 2
1.2 BiCMOS Device Technology 4
1.3 BiCMOS Process Technology 7
1.4 BiCMOS Costs 9
1.5 Applications 11
1.5.1 Memories 12
1.5.2 Semi-Custom 13
1.5.3 Microprocessors 15
1.5.4 Analog/Digital Systems 15
1.6 Projections 16
1.7 Summary 17
1.8 References 17
Chapter 2. Device Design, Optimization and Scaling
1. Teplik (Motorola Inc.)
2.0 Introduction 21
2.1 MOS Devices 22
2.1.1 Channel Considerations 23
2.1.2 Source/Drain Design Considerations 30
2.1.3 Parasitic Devices 32
2.2 Bipolar Devices 34
2.2.1 Base Design Issues 34
2.2.2 Emitter Design Issues 36
2.2.3 Collector Design Issues 39
2.2.4 Horizontal Design Issues 42
2.2.5 Extrinsic Device Issues 45
2.2.6 Summary 45
2.3 BiCMOS Device Synthesis 47
2.3.1 Front-end Design 48
2.3.2 BiCMOS Device Compromises 49
2.4 Design Methodology 53
2.4.1 Synthesis versus Analysis 53
2.4.2 Response Surface Methodology 54
2.4.3 Circuit Design Considerations 59
2.5 Device Scaling 61
viii
2.5.1 MOS Scaling 61
2.5.2 Bipolar Scaling 62
2.5.3 BiCMOS Scaling Considerations 64
2.6 References 65
Chapter 3. BiCMOS Process Technology
R.H. Eklund, R.A. Haken, R.H. Havemann, L.N. Hutter
(Texas Instruments, Inc.)
3.0 Introduction 73
3.1 Evolution of BiCMOS From a CMOS Perspective 75
3.2 BiCMOS Isolation Considerations 79
3.2.1 Latchup 79
3.2.2 Buried Layers 80
3.2.3 Epitaxy and Autodoping 81
3.2.4 Parasitic Junction Capacitance 82
3.2.5 Trench Isolation 82
3.2.6 Active Device Isolation 83
3.3 CMOS Well and Bipolar Collector Process Tradeoffs 85
3.4 CMOS Processing Considerations 89
3.4.1 CMOS Threshold Voltage Considerations
and Adjustment 90
3.4.2 SourcelDrain Processing and Channel Profiles 90
3.4.3 Relationship Between Transistor Performance
and Manufacturing Control 95
3.5 Bipolar Process Options and Tradeoffs 96
3.5.1 Base Design Options 98
3.5.2 Emitter Design Options 98
3.5.3 Collector Design Options 99
3.6 Interconnect Processes for Submicron BiCMOS 101
3.6.1 Silicidation 101
3.6.2 Local Interconnect 104
3.6.3 Planarization and Metallization 107
3.7 Example Submicrometer BiCMOS Process Flow for
5V Digital Applications 110
3.7.1 Starting WaferandN+BuriedLayerFormation 111
3.7.2 Epitaxial Layer Deposition 112
3.7.3 Twin-well Formation 112
3.7.4 Active Region and Channel Stop Formation 113
3.7.5 Deep N+ Collector and Base Formation 113
3.7.6 Polysilicon Emitter Formation 114
3.7.7 Gate and LDD Formation 115
3.7.8 Sidewall Oxide and Final Junction Formation 115
3.7.9 Silicide and Local Interconnect Process 116
3.7.10 Multilevel Metal (MLM) Processing 117
ix
3.8 Process Changes for O.5Jl BiCMOS 118
3.8.1 Isolation 118
3.8.2 CMOS Transistor Formation 118
3.8.3 NPN Profile Optimization 118
3.8.4 Addition of a Vertical PNP 119
3.8.5 Multilevel Metallization 119
3.9 Analog BiCMOS Process Technology 120
3.9.1 Analog BiCMOS Evolution 120
3.9.2 Analog BiCMOS Process Design Considerations 121
3.9.3 Analog BiCMOS Process Integration Discussion 125
3.9.4 Sample Analog BiCMOS Process 128
3.9.5 Future Process Issues in Analog BiCMOS 133
3.10 Acknowledgements 135
3.11 References 135
Chapter 4. Process Reliability
R. Lahri, J. Shibley, D. Merrill, H. Wang, B. Bastani
(National Semiconductor Corporation)
4.1 Introduction 141
4.2 Reliability by Design 141
4.2.1 Reliability and Performance Tradeoffs 142
4.2.2 Monitoring Reliability 143
4.3 Built-In Immunity to Soft Errors 146
4.3.1 Alpha Particle Induced Charge Collection 147
4.3.2 Role of Epitaxial Layer and Buried Layer 148
4.3.3 Soft Errors in BiCMOS SRAMs 150
4.3.4 Other Protection Techniques 150
4.4 Gate Oxide Integrity and Hot Electron Degradation in
MOSFETs 151
4.4.1 Gate Oxide Integrity 152
4.4.2 DC Hot Electron Characteristics 153
4.4.3 Role of Backend Processing 156
4.4.4 AC Hot Carrier Degradation 156
4.5 Hot Carrier Effects in Bipolar Devices 159
4.5.1 Device Instability Due to High Injection Forward Bias 160
4.5.2 Device Instability Due to Reverse Biasing ofE-B
Junction 160
4.5.3 Charge to Degradation Model 161
4.5.4 AC vs DC Stressing 162
4.6 Electromigration 163
4.6.1 Multilayer Interconnect Systems 164
4.6.2 Electromigration in Multilayer Interconnect Systems 164
4.6.3 Role of Passivation Films 166
4.7 Latchup in BiCMOS Circuits 166
x
4.7.1 Latchup Phenomenon 166
4.7.2 Latchup in Merged Devices 169
4.8 ESD Protection 170
4.8.1 ESD Models 171
4.8.2 ESD Failure Mechanisms 173
4.8.3 ESD Solutions 174
4.9 Summary 177
4.10 References 179
Chapter 5. Digital Design
P. Raje, (Hewlett-Packard)
5.0 Introduction 183
5.1 Delay Analysis 185
5.1.1 Equivalent Circuit 186
5.1.2 Delay Expression 188
5.1.3 Peak Collector Current 191
5.1.4 Model Verification 192
5.2 Gate Design 193
5.2.1 BiCMOS Sizing Plane 194
5.2.2 Gate Delay Contours 195
5.2.3 Gate Design in The Sizing Plane 198
5.3 Performance Comparisons 201
5.3.1 Gate Comparison Methodology 201
5.3.2 Technology Comparison Methodology 204
5.4 Device Scaling 206
5.4.1 Scaling Analysis Framework 208
5.4.2 Optimum BiCMOS Scaling 212
5.5 MBiCMOS 217
5.5.1 Gate Description 218
5.5.2 Gate Performance 221
5.6 References 224
Chapter 6. BiCMOS Standard Memories
H.V. Tran, P.K. Fung, D.B. Scott, A.H. Shah
(fexas Instruments, Inc.)
6.0 Introduction to BiCMOS Memory ICs 229
6.1 Architecture and Functional Blocks 230
6.1.1 Static Random Access Memory 230
6.1.2 Dynamic Random Access Memory 232
6.2 BiCMOS Implementation 234
6.3 Input Buffers 234
6.3.1 ECL Input Buffer 234
6.3.2 TTL Input Buffer 239
xi
6.3.3 Other Input Buffer Designs 243
6.4 Level Conversion 244
6.4.1 ECL to CMOS 244
6.4.2 CMOS to ECL 246
6.4.3 BiCMOS to CMOS 246
6.5 Decoding 247
6.5.1 ECL Decode 247
6.5.2 CMOS Decode 249
6.5.3 BiCMOS Decode 251
6.6 Memory Cells 252
6.6.1 Bipolar Memory Cell 252
6.6.2 CMOS Six Transistor Memory Cell 254
6.6.3 Four Transistor. Two Resistor Memory Cell 255
6.6.4 Merged Bipolar/CMOS Memory Cell 256
6.7 Sensing 257
6.7.1 Standard Sensing Operation 257
6.7.2 Individual Column Amplification 258
6.7.3 DRAM's Amplification Scheme 260
6.7.4 Final Sense Amplification 261
6.8 Output Buffer 263
6.8.1 ECL Output Buffer 263
6.8.2 TTL Output Buffer 264
6.8.3 CMOS Output Buffer 265
6.9 General Noise Considerations 266
6.10 Summary and Discussion of BiCMOS Implementation 266
6.11 Outlook 268
6.12 References 268
Chapter 7. Testing
M.E. Levitt (Sun Microsystems). K. Roy (Texas Instruments)
7.1 Introduction 271
7.2 Test Strategies 272
7.2.1 Stuck-At 272
7.2.2Iddq 272
7.2.3 Delay Fault Testing 273
7.3 BiCMOS Logic Families 274
7.3.1 Standard BiCMOS 274
7.3.2 BiNMOS 275
7.3.3 Full-rail BiCMOS 275
7.3.4 CBiCMOS 276
7.4 Fault Modeling 276
7.5 Simulation Study Results 277
7.6 Design-for-Testability 281
7.6.1 Circuit Level DFT 284