Design Techniques for 50GS/s ADC Yida Duan Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-173 http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-173.html December 1, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement The authors would like to thank the sponsors, faculty, staff, and students of Berkeley Wireless Research Center for support, and the TSMC University Shuttle Program for chip fabrication. Design Techniques for 50GS/s ADCs Abstract In recent years, the explosive growth in data traffic has led to the demand for extremely high sample-rate ADCs. For example, high performance receivers for backplane channels and multi- mode fibers with DSP-based channel equalization or electronic dispersion compensation (EDC) rely on ADCs with sampling rates of greater than 10GS/s [1], [2]. Similarly, emerging 100Gbps/400Gbps coherent fiber optics receivers with high degree of modulation require even higher sampling speed – greater than 50GS/s [3], [4]. In these applications, moderate ENOB between 4 and 6 are required. In this report, the design techniques for building 6b 50GS/s ADC is presented. To demonstrate proposed circuits and design techniques, a 12.8GS/s 32-way hierarchically time-interleaved quarter ADC prototype is fabricated in 65nm CMOS. It achieved 4.6 ENOB and 25GHz 3dB effective resolution bandwidth (ERBW). As described in Section VII, the layout of the prototype is taken particular care so that it can be straight-forwardly expanded 51.2GS/s via additional interleaving without significantly impacting ERBW and FOM. N Clk gen. A/D Input 50Ω Term. A/D Broadband buffer Fig. 1. Conventional time-interleaved ADC 2 I. Introduction These applications typically require relatively modest resolution – ~4-6 ENOB. Most state-of- art solutions with a high degree of interleaving achieve either relatively degraded energy efficiency [3], [4] or lower-than-Nyquist 3dB ERBW [6]. These tradeoffs arise due to several issues with conventional time-interleaved ADC architectures. First, in order to isolate the capacitive parasitics of the samplers and mitigate kickback, such ADCs (Fig. 1) often consist of a broadband input buffer that directly drives all of the parallel sampling switches [5]. Since all the parallel switches directly sample the continuously changing output voltage of the buffer (or the input voltage itself, if a buffer is not used), the jitter of the clocks driving every one of these switches will degrade SNDR at high frequencies. Thus, to meet the stringent jitter required to achieve extremely high ERBW, an excessive amount of power must be spent in the clock distribution network to keep these clock signals as clean as possible. Furthermore, because this input signal (buffered or not) must fan out to all of the sub-ADCs, this routing may add significant parasitic capacitance, especially if the number of sub-ADCs is large. This will either limit the front-end bandwidth (and hence the bandwidth of the overall ADC) or cause excessive power consumption for the buffer. Finally, the input buffer must charge each sampling capacitor through the series resistance of the sampling switch during track mode, thus further limiting the bandwidth and the sampling rate of the converter. To overcome these issues, we leverage a hierarchical sampling architecture [3], [7], [8] and propose a cascode sampling circuit. Section II reviews hierarchical sampling as an attractive architecture to alleviate the need for distributing a large number of low-jitter clocks. Then, Section III. proposes and introduces a cascode sampling circuit to overcome the speed limitations of traditional samplers based on series switches. In Section IV, a general power optimization method 3 for hierarchical sampling network with cascode sampler is presented. Section V describes the circuit level implementations of the building blocks used in the design, including the cascode sampler, clock generation circuits, and sub-ADCs. Finally, measurement results are presented in Section VI, and the paper is concluded in Section VII. Φ <0:3> FD1B 2B ÷4 CLK 90º in PI2<0> PI2<1> PI2<2> PI2<3> CLK 0º PI in 1 FD1A FD2<0> FD2<1> FD2<2> FD2<3> ÷4 ÷8 ÷8 ÷8 ÷8 Dcourtrye-ccyticolne Φ<0:3> 2A Φ<0:7> 3A ΦBC,A Φ<0:7> 3B ΦBC,B <0:7> Φ3C ΦBC,C Φ<0:7> 3D ΦBC,D 1> 3 : 4 A/D 2 < C D A A/D - R Φ 1 3> SA 2 A/D : 6 1 < C Input A/D D A > R- 50Ω 15 A A/D : S Term. 8 Rank-1 < C D A/D A - R 7> A A/D 0: S < C D A A/D - R Rank-2 Rank-3 A S Fig. 2. ADC architecture Track Hold Φ 1 Φ <0> 2A Φ <1> 2A Φ <2> 2A Φ <3> 2A Φ <0> 3A Φ <1> 3A Fig. 3. Timing diagram of the hierarchical sampler 4 II. Hierarchically Time-Interleaved Sampling As mentioned earlier and highlighted in Fig. 2 (ADC architecture) and Fig.3 (timing diagram), this design adopts a hierarchical sampling approach with a 4-way interleaved front-end sample- and-hold circuit in order to reduce the number of low-jitter clocks that must be generated and distributed [3], [7]. Once the continuously changing input voltage is sampled and held by the frond-end (Rank-1) sampler, the output of this sampler is a constant voltage during the entire hold time. Thus, any perturbation of sampling instance at the Rank-2 sampler does not directly translate into voltage errors as long as it is within this hold window, allowing the jitter requirements for the Rank-2 and subsequent ranks of samplers to be greatly relaxed. As a result, the only jitter-critical clocks in the entire sampler system are the 4 12.8GS/s clocks of the font-end samplers (Rank-1). An additional benefit of hierarchical sampling is the greatly reduced signal routing at the output of the front-end buffer; since it can limit the input bandwidth of the entire ADC, the bandwidth of this buffer is critical. As opposed to conventional time-interleaved ADCs where the input buffer must fan-out to all sub-ADCs (in this design, 128 sub-ADCs), the front-end sampler drives only the next rank of samplers/de-multiplexors (in this case, a single Rank-2 demux.), thus substantially reducing the parasitic capacitance at the output of the frond-end sampler. III. Cascode Sampler The hierarchical sampling architecture has significant benefits for high sample-rate applications, but its overall performance is still limited by the sampler circuits themselves. In particular, as we will describe next, conventional sampling circuits suffer from bandwidth limitations that can compromise either the overall bandwidth or the energy-efficiency of the entire ADC. A conventional sampling circuit (Fig. 4a) consists of a source follower buffer combined with a series sampling switch. The final load capacitance (cid:1829) is thus driven by the sum of the output (cid:3013) 5 resistance of the source follower and the switch resistance. This series configuration of resistors makes the conventional sampling circuit very power-inefficient in high speed designs. To make matters worse, when the sampling period approaches 4 FO4 (i.e., 4 times the fan-out-of-4 delay of an inverter) – i.e., at ~10GS/s and above – constant-V sampling techniques [9] do not perform GS well because of the long rise time of the switch control signal. The circuit’s settling time must therefore be maintained even under the worst-case (signal-dependent) switch resistance, leading to substantially increased buffer power consumption. Sasmwiptclihng + Vx- 1/gds2 + V Φ o Vin M1 M2 Vout Vi +- Cg1 gm1∙ Vx Cs1+2C+Cs2d+3Cg2/ -CL+Cd2+Cg2/2 Vb M3 CL (a) -g · V m2 x V Φ M3 x + V V o out Φ M2 CL Vi +- Cg1 gm1· Vi Cg2+Cs2+Cd1 1/gds3 -CL+Cd2+Cd3+Cg3/2 V M in 1 (b) Fig. 4. Schematic and small-signal model of (a) conventional sampler (b) cascode sampler In order to mitigate the penalty caused by the series resistance of the sampling switch and hence improve the tradeoff between sampling speed and power consumption, we propose a cascode sampling circuit that merges the sampling operation into the buffer itself [10]. A single-ended version of the proposed cascode sampling circuit is shown in Fig. 4b. During the track phase when Φ is high, M form a cascoded common-source amplifier, with the PMOS M acting as a triode 1,2,3 3 load resistor. M and M are sized to provide a DC gain of ~1. During the hold phase when Φ is 1 3 low, both M and M are cut-off and the output voltage is held on (cid:1829) . The key advantage of this 2 3 (cid:3013) design is that as long as the cascode device (M ) operates in saturation and has sufficiently high 2 6 (cid:1858) relative to the operating rate, the dominant pole of the circuit is set only by the output node (cid:3021) resistance and capacitance. In other words, in contrast to the traditional sampling circuit, the addition of the sampling switch does not directly affect the settling time. In order to more rigorously highlight the benefits of a cascode sampling circuit over the conventional sampling circuit, we can use small signal models (Fig. 4) of both designs to analyze the trade-off between the input device (cid:1859) and the dominant pole location. In this technology, the (cid:3040) dominant pole for the cascode sampling circuit is: (cid:1859) (cid:3031)(cid:3046)(cid:2871) (cid:1842) (cid:3404) (cid:3398) (cid:4666)(cid:2778)(cid:4667) (cid:2869) (cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) ⁄2 (cid:3013) (cid:3031)(cid:2870) (cid:3031)(cid:2871) (cid:3034)(cid:2871) To provide some numerical comparisons, we will assume that the (cid:1858) of the PMOS transistors is (cid:3021) half that of the NMOS transistors, and that the ratio between (cid:1829) and (cid:1829) is 1 for all transistors.1 (cid:3031),(cid:3046) (cid:3034) We will further assume (as is the case in our particular technology) that the maximum triode (cid:1859) (cid:3031)(cid:3046) of a transistor is roughly twice the maximum saturation (cid:1859) . With all of these assumptions (cid:3040) combined, if (cid:1858) is the unity current-gain frequency of all the NMOS transistors, then (cid:1859) ⁄(cid:1829) (cid:3404) (cid:3021) (cid:3031)(cid:3046)(cid:2871) (cid:3034)(cid:2871) 2∙2(cid:2024)(cid:1858) . Finally, (cid:1859) is equal to (cid:1859) for unity DC gain. With these assumptions, (1) can be (cid:3021) (cid:3031)(cid:3046)(cid:2871) (cid:3040)(cid:2869) rewritten as: 2(cid:2024)(cid:1858) (cid:3021) (cid:1842) (cid:3404) (cid:4666)(cid:2779)(cid:4667) (cid:2869) 2(cid:2024)(cid:1858) (cid:1829) 5 (cid:3021) (cid:3013) (cid:3397) (cid:1859) 2 (cid:3040)(cid:2869) We next examine the dominant pole of the traditional sampler, which can be approximated as: 1 (cid:1842) ≅ (cid:4666)(cid:2780)(cid:4667) (cid:2869) (cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) (cid:1829) (cid:3397)(cid:1829) (cid:3397)(cid:1829) ⁄2 (cid:3034)(cid:2869) (cid:3046)(cid:2869) (cid:3031)(cid:2871) (cid:3031)(cid:2870) (cid:3046)(cid:2870) (cid:3034)(cid:2870) (cid:3013) (cid:3013) (cid:3031)(cid:2870) (cid:3034)(cid:2870) (cid:3397) (cid:1859) (cid:1859) (cid:3040)(cid:2869) (cid:3031)(cid:3046)(cid:2870) 1 In order to simplify the derivation, it is assumed that C equals C for the conventional sampler circuit (Fig. 4a). g3 g1 Although there may be some slight speed advantages to making device M smaller, headroom limitations – especially 3 in advanced processes with low supply voltage – often restrict the degree to which M3 can be downsized. 7 Utilizing the same assumptions as stated earlier for the cascode sampler, (3) becomes: 2(cid:2024)(cid:1858) (cid:3021) (cid:1842) (cid:3404) (cid:4666)(cid:2781)(cid:4667) (cid:2869) 15 1 2(cid:2024)(cid:1858) (cid:1829) (cid:3397)3(cid:2010) (cid:3397)(cid:3436) (cid:3397)1(cid:3440) (cid:3021) (cid:3013) 4 2(cid:2010) (cid:1859) (cid:3040)(cid:2869) Where (cid:2010) (cid:3404) (cid:1849) /(cid:1849) is the ratio of the widths of M and M . The dominant pole achieves its (cid:2870) (cid:2869) 2 1 maximum value when (cid:2010) (cid:3404) 1⁄(cid:3493)3(cid:1859) ⁄(cid:2024)(cid:1858) (cid:1829) , and this optimal (cid:1842) is: (cid:3040)(cid:2869) (cid:3021) (cid:3013) (cid:2869) 2(cid:2024)(cid:1858) (cid:3021) (cid:1842) (cid:3404) (cid:4666)(cid:2782)(cid:4667) (cid:2869) 15 2(cid:2024)(cid:1858) (cid:1829) 3 2(cid:2024)(cid:1858) (cid:1829) (cid:3397) (cid:3021) (cid:3013) (cid:3397)2(cid:3495) ∙ (cid:3021) (cid:3013) 4 (cid:1859) 2 (cid:1859) (cid:3040)(cid:2869) (cid:3040)(cid:2869) With these expressions (Eq. (2) & (5)) in hand, Fig. 5 compares the trade-off between (cid:1859) and the (cid:3040) dominant pole for both designs. Notice that the advantage of the cascode sampler is most apparent when the circuit bandwidth approaches a significant fraction of f (but remains well below f so T T that the source node of the cascode is still relatively fast). Specifically, for P ≈⅛·2πf – which is 1 T the target for the Rank-1 sampler in our ADC design – the conventional sampler requires more than four times higher (cid:1859) (and hence power) than the proposed cascode sampler. (cid:3040)  Conventional sampler Cascode L C  sampler T f  2 Design / 1 m Point g        P /2f 1 T Fig. 5. Comparison between conventional and cascode sampler 8

Design Techniques for 50GS/s ADC

Similar Design Techniques for 50GS/s ADC