Understanding Delta-Sigma Data Converters

570 Pages·2017·8.044 MB·English

by  Shanthi Pavan,  Richard Schreier,  Gabor C. Temes

UNDERSTANDING
DELTA-SIGMA DATA
CONVERTERS
SECOND EDITION
SHANTHI PAVAN
RICHARD SCHREIER
GABOR C. TEMES
IEEE Press SeriesonMicroelectronicSystems
Copyright © 2017 by The Institute of Electrical and Electronics Engineers, Inc.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
Published simultaneously in Canada.
Library of Congress Cataloging-in-Publication Data is available.
ISBN: 978-1-119-25827-8
Printed in the United States of America.
CONTENTS
Preface xiii
1 TheMagicofDelta-SigmaModulation 1
1.1 TheNeedforOversamplingConverters 1
1.2 NyquistandOversamplingConversionbyExample 3
1.2.1 TheCoffeeShopProblem 4
1.2.2 TheDictionaryProblem 6
1.3 Higher-OrderSingle-StageNoise-ShapingModulators 11
1.4 Multi-StageandMulti-QuantizerDelta-SigmaModulators 12
1.5 MismatchShapinginMulti-BitDelta-SigmaModulators 14
1.6 Continuous-TimeDelta-SigmaModulation 15
1.7 BandpassDelta-SigmaModulators 17
1.8 IncrementalDelta-SigmaConverters 18
1.9 Delta-SigmaDigital-to-AnalogConverters 18
1.10 DecimationandInterpolation 19
1.11 SpecificationsandFiguresofMerit 19
1.12 EarlyHistory,Performance,andArchitecturalTrends 21
References 25
2 Sampling,Oversampling,andNoise-Shaping 27
2.1 AReviewofSampling 28
2.2 Quantization 30
2.2.1 QuantizerModeling 35
2.2.2 OverloadedQuantizers 37
2.2.3 QuantizerModelingwithTwoInputs 38
2.3 QuantizationNoiseReductionbyOversampling 39
2.4 Noise-Shaping 42
2.4.1 TheEffectsofFiniteDCGainoftheIntegrator 50
2.4.2 EffectofQuantizerNonidealities 50
2.4.3 TheSingle-BitFirst-OrderDelta-SigmaModulator 51
2.5 NonlinearAspectsoftheFirst-OrderDelta-SigmaModulator 52
2.6 MOD1withDCExcitation 54
2.6.1 IdleToneGeneration 55
2.6.2 StabilityofMOD1 57
2.6.3 Dead-Zones 57
2.7 AlternativeArchitectures: TheError-FeedbackStructure 60
2.8 TheRoadAhead 60
References 61
3 Second-OrderDelta-SigmaModulation 63
3.1 SimulationofMOD2 67
3.2 NonlinearEffectsinMOD2 70
3.2.1 Signal-DependentQuantizerGain 70
3.3 StabilityofMOD2 73
3.3.1 Dead-Zones 75
3.4 AlternativeSecond-OrderModulatorStructures 77
3.4.1 TheBoser–WooleyModulator 77
3.4.2 TheSilva–SteensgaardStructure 78
3.4.3 TheError-FeedbackStructure 79
3.4.4 TheNoise–CoupledStructure 79
3.5 GeneralizedSecond-OrderStructures 80
3.5.1 OptimalSecond-OrderModulator 81
3.6 Conclusions 82
References 82
4 High-OrderDelta-SigmaModulators 83
4.1 Signal-DependentStabilityofDelta-SigmaModulators 85
4.1.1 EstimatingMaximumStableAmplitude 90
4.2 ImprovingMSAinHigh-OrderDelta-SigmaConverters 92
4.3 SystematicNTFDesign 95
4.4 NoiseTransferFunctionswithOptimallySpreadZeros 97
4.5 FundamentalAspectsofNoiseTransferFunctions 98
4.5.1 TheBodeSensitivityIntegral 98
4.6 High-OrderSingle-BitDelta-SigmaDataConverters 100
4.7 LoopFilterTopologiesforDiscrete-TimeDelta-SigmaConverters 104
4.7.1 Loop Filters with Distributed Feedback: The CIFB and
CRFBFamilies 104
4.7.2 Loop Filters with Distributed Feedforward and Input
Coupling: TheCIFFandCRFFStructures 111
4.7.3 LoopFilterswithFeedforwardandMultipleFeedback: The
CIFF-BStructure 113
4.8 State-SpaceDescriptionofDelta-SigmaLoops 114
4.9 Conclusions 115
References 115
5 Multi-StageandMulti-QuantizerDelta-SigmaModulators 117
5.1 Multi-StageModulators 117
5.1.1 TheLeslie–SinghStructure[1] 118
5.2 Cascade(MASH)Modulators 120
5.3 NoiseLeakageinCascadeModulators 123
5.4 TheSturdy-MASHArchitecture 126
5.5 Noise-CoupledArchitectures 128
5.6 Cross-CoupledArchitectures 131
5.7 Conclusions 131
References 133
6 Mismatch-Shaping 135
6.1 TheMismatchProblem 135
6.2 RandomSelectionandRotation 136
6.3 ImplementationofRotation 141
6.4 AlternativeMismatch-ShapingTopologies 145
6.4.1 ButterflyShuffler 145
6.4.2 A-DWAandBi-DWA 146
6.4.3 Tree-StructuredESL 148
6.5 High-OrderMismatch-Shaping 151
6.5.1 Vector-BasedMismatch-Shaping 151
6.5.2 TreeStructure 154
6.6 Generalizations 156
6.6.1 Tri-LevelElements 156
6.6.2 Non-UnitElements 157
6.7 Transition-ErrorShaping 158
6.8 Conclusions 162
References 162
7 CircuitDesignforDiscrete-TimeDelta-SigmaADCs 165
7.1 SCMOD2: ASecond-OrderSwitched-CapacitorADC 165
7.2 High-LevelDesign 166
7.2.1 NTFSelection 166
7.2.2 RealizationandDynamic-RangeScaling 167
7.3 Switched-CapacitorIntegrator 168
7.3.1 IntegratorVariations 171
7.4 CapacitorSizing 174
7.5 InitialVerification 176
7.6 AmplifierDesign 178
7.6.1 AmplifierGain 180
7.6.2 CandidateAmplifier 183
7.7 IntermediateVerification 186
7.8 SwitchDesign 191
7.9 ComparatorDesign 191
7.10 Clocking 195
7.11 Full-SystemVerification 197
7.12 High-OrderModulators 201
7.12.1 Architecture 201
7.12.2 CapacitorSizing 201
7.12.3 CombiningtheNoisefromMultipleSCBranches 203
7.13 Multi-BitQuantization 203
7.14 SwitchDesignRevisited 207
7.15 DoubleSampling 209
7.16 Gain-BoostingandGain-Squaring 211
7.17 Split-SteeringandAmplifierStacking 212
7.18 NoiseinSwitched-CapacitorCircuits 217
7.19 Conclusions 221
References 221
8 Continuous-TimeDelta-SigmaModulation 223
8.1 CT-MOD1 224
8.2 STFofCT-MOD1 230
8.2.1 SummaryofCT-MOD1 233
8.3 Second-OrderContinuous-TimeDelta-SigmaModulation 234
8.3.1 InfluenceoftheDACPulseShape 237
8.4 High-OrderContinuous-TimeDelta-SigmaModulators 239
8.4.1 InfluenceofDACPulseShape[4] 241
8.5 Loop-FilterTopologies 246
8.5.1 TheCIFBFamily 246
8.5.2 TheCIFFFamily 248
8.5.3 TheCIFF-BFamily 249
8.6 Continuous-TimeDelta-SigmaModulatorswithComplexNTFZeros 249
8.7 ModelingofContinuous-TimeDelta-SigmaModulatorsforSimulation 250
8.8 Dynamic-RangeScaling 253
8.9 DesignExample 255
8.10 Conclusions 258
References 258
9 NonidealitiesinContinuous-TimeDelta-SigmaModulators 259
9.1 ExcessLoopDelay 259
9.1.1 CT-MOD1: TheFirst-OrderContinuous-TimeDelta-Sigma
Modulator 260
9.1.2 CT-MOD2 : The Second-Order Continuous-Time Delta-
SigmaModulator 263
9.1.3 ExcessDelayCompensationinHigh-OrderContinuous-Time
Delta-SigmaModulatorswithArbitraryDACPulseShapes
[2,3] 267
9.1.4 Summary 270
9.2 Time-ConstantVariationsoftheLoopFilter 271
9.3 ClockJitterinDelta-SigmaModulators 273
9.3.1 TheDiscrete-TimeCase 273
9.3.2 ClockJitterinContinuous-TimeDelta-SigmaModulators 274
9.3.3 Clock Jitter in Single-Bit Continuous-Time Delta-Sigma
Modulators 278
9.3.4 Continuous-TimeDelta-SigmaModulatorswithRZDACs 280
9.3.5 RealClockSourcesandPhaseNoise 282
9.4 AddressingClockJitterinContinuous-TimeDelta-SigmaModulators 285
9.5 MitigatingClockJitterUsingFIRFeedback 287
9.6 ComparatorMetastability 293
9.7 Conclusions 298
References 298
10 CircuitDesignforContinuous-TimeDelta-SigmaModulators 301
10.1 Integrators 302
10.1.1 TheSingle-StageOTA-RCIntegrator 304
10.2 TheMiller-CompensatedOTA-RCIntegrator 305
10.3 TheFeedforward-CompensatedOTA-RCIntegrator 306
10.4 StabilityofFeedforwardAmplifiers 309
10.5 DeviceNoiseinContinuous-TimeDelta-SigmaModulators 312
10.5.1 ThermalversusQuantizationNoise 315
10.6 ADCDesign 316
10.7 FeedbackDACDesign 320
10.7.1 ResistiveDACs 322
10.7.2 Return-to-ZeroandReturn-to-OpenDACs 325
10.7.3 Current-SteeringDACs 326
10.7.4 Switched-CapacitorDACs 328
10.8 SystematicDesignCentering 331
10.8.1 Closed-LoopFitting 336
10.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma
Modulators 338
10.9.1 CircuitTechniquestoImproveLoop-FilterLinearity 345
10.10 CaseStudyofa16-BitAudioContinuous-TimeDelta-SigmaModulator346
10.10.1 ChoiceofNumberofTapsintheFIRDAC 349
10.10.2 State-SpaceModelingandSimulationwithanFIRDAC 350
10.10.3 EffectofTime-ConstantVariations 352
10.10.4 ModulatorArchitecture 352
10.10.5 OpampDesign 353
10.10.6 ADCandFIRDACs 357
10.10.7 DecimationFilter 358
10.11 MeasurementResults 358
10.12 Summary 359
References 360
11 BandpassandQuadratureDelta-SigmaModulation 363
11.1 TheNeedforBandpassConversion 363
11.2 SystemOverview 366
11.3 BandpassNTFs 367
11.3.1 N-PathTransformation 368
11.4 ArchitecturesforBandpassDelta-SigmaModulators 372
11.4.1 TopologyChoices 372
11.4.2 ResonatorImplementations 375
11.5 BandpassModulatorExample 380
11.5.1 LNA 382
11.5.2 Attenuator 383
11.5.3 Amplifiers 385
11.5.4 Measurements 387
11.6 QuadratureSignals 391
11.6.1 QuadratureMixing 391
11.6.2 QuadratureFilters 392
11.7 QuadratureModulation 396
11.8 PolyphaseSignalProcessing 402
11.9 Conclusions 404
References 405
12 IncrementalAnalog-to-DigitalConverters 407
12.1 MotivationandTrade-Offs 407
12.2 AnalysisandDesignofSingle-StageIADCs 408
12.3 DigitalFilterDesignforSingle-StageIADCs 411
12.4 Multiple-StageIADCsandExtendedCountingADCs 415
12.5 IADCDesignExamples 416
12.5.1 Third-OrderSingle-BitIADC 416
12.5.2 Two-StepIADC 420
12.6 Conclusions 422
References 423
13 Delta-SigmaDACs 425
13.1 SystemArchitecturesforDelta-SigmaDACs 425
13.2 LoopConfigurationsforDelta-SigmaDACs 427
13.2.1 Single-StageDelta-SigmaLoops 428
13.2.2 TheError-FeedbackStructure 429
13.2.3 Cascade(MASH)Structures 430
13.3 Delta-SigmaDACsUsingMulti-BitInternalDACs 431
13.3.1 Dual-TruncationDACStructures 432
13.3.2 Multi-bitDelta-SigmaDACswithMismatchErrorShaping 434
13.3.3 DigitalCorrectionofMulti-BitDelta-SigmaDACs 436
13.3.4 ComparisonofSingle-BitandMulti-BitDelta-SigmaDACs 437
13.4 InterpolationFilteringforDelta-SigmaDACs 438
13.5 AnalogPost-FiltersforDelta-SigmaDACs 441
13.5.1 AnalogPost-FilteringinSingle-BitDelta-SigmaDACs 441
13.5.2 AnalogPost-FilteringinMulti-BitDelta-SigmaDACs 447
13.6 Conclusions 449
References 449
14 InterpolationandDecimationFilters 451
14.1 InterpolationFiltering 452
14.2 ExampleInterpolationFilter 456
14.3 DecimationFiltering 461
14.4 ExampleDecimationFilter 463
14.5 HalfbandFilters 467
14.5.1 SaramäkiHalfbandFilter 469
14.6 DecimationforBandpassDelta-SigmaADCs 471
14.7 FractionalRateConversion 472
14.7.1 Decimationby1.5 472
14.7.2 Sample-RateConversion 475
14.8 Summary 480
References 480
A SpectralEstimation 483
A.1 Windowing 484
A.2 ScalingandNoiseBandwidth 488
A.3 Averaging 491
A.4 AnExample 493
A.5 MathematicalBackground 495
References 498
B TheDelta-SigmaToolbox 499
C LinearPeriodicallyTime-Varying
Systems 539
C.1 LinearityandTime(In)variance 539
C.2 LinearTime-VaryingSystems 541
C.3 LinearPeriodicallyTime-Varying(LPTV)Systems 543
C.4 LPTVSystemswithSampledOutputs 547
C.4.1 MultipleInputs 555
C.4.2 AliasRejectioninContinuous-TimeDelta-SigmaModulators
Revisited 556
References 559
Index 561