Xilinx Constraints Guide PDF
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Constraints Guide UG625(v. 13.3)October19,2011 Xilinxisdisclosingthisuserguide,manual,releasenote,and/orspecification(the“Documentation”)toyou solelyforuseinthedevelopmentofdesignstooperatewithXilinxhardwaredevices. Youmaynotreproduce, distribute,republish,download,display,post,ortransmittheDocumentationinanyformorbyanymeans including,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withouttheprior writtenconsentofXilinx. XilinxexpresslydisclaimsanyliabilityarisingoutofyouruseoftheDocumentation. Xilinxreservestheright,atitssolediscretion,tochangetheDocumentationwithoutnoticeatanytime. Xilinx assumesnoobligationtocorrectanyerrorscontainedintheDocumentation,ortoadviseyouofanycorrections orupdates. Xilinxexpresslydisclaimsanyliabilityinconnectionwithtechnicalsupportorassistancethatmaybe providedtoyouinconnectionwiththeInformation. THEDOCUMENTATIONISDISCLOSEDTOYOU“AS-IS”WITHNOWARRANTYOFANYKIND.XILINX MAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDING THEDOCUMENTATION,INCLUDINGANYWARRANTIESOFMERCHANTABILITY,FITNESSFORA PARTICULARPURPOSE,ORNONINFRINGEMENTOFTHIRD-PARTYRIGHTS.INNOEVENTWILL XILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY,SPECIAL,ORINCIDENTAL DAMAGES,INCLUDINGANYLOSSOFDATAORLOSTPROFITS,ARISINGFROMYOURUSEOFTHE DOCUMENTATION. ©Copyright2002-2011XilinxInc. AllRightsReserved. XILINX,theXilinxlogo,theBrandWindowandother designatedbrandsincludedhereinaretrademarksofXilinx,Inc. Allothertrademarksarethepropertyoftheir respectiveowners. ThePowerPCnameandlogoareregisteredtrademarksofIBMCorp.,andusedunderlicense. Allothertrademarksarethepropertyoftheirrespectiveowners. Revision History Date Version Revision 03/01/2011 13.1 AddedVCCAUX_IOandMARK_DEBUGconstraints. 06/22/2011 13.2 AddedSpartan®-6tolistofsupporteddeviceswhereappropriate. ForPULLUP(Pullup)constraint,addedinformationthatNGDBuildignoresthefollowing: •DEFAULTKEEPER=FALSE•DEFAULTPULLUP=FALSE•DEFAULTPULLDOWN =FALSE ForIODELAY_GROUP(IODELAYGroup)constraint,addedinformationunderLimitations withLOCandArchitectureSupport ForAreaGroup(AREA_GROUP)constraint,addedNote:Allcomponentscanbeconstrained bytheCLOCKREGIONrangeexceptIOBandBUF. ForCONFIG_MODE(ConfigurationMode)constraint,addednewarchitecturesupport andnewvalues. ForBEL(BEL)constraint,removedVHDLexample. 10/19/2011 13.3 Removedsentence“TheRISINGandFALLINGkeywordsmayalsobeusedwithTNM.” AddedDIFF_TERMsupportforVirtex®-6devices. ChangeddefaultunitsforbothINPUT_JITTERandSYSTEM_JITTERconstraintsfromps tons. AddedinformationthatOFFSETConstraintsdonotallowpredefinedgroups. UpdatedPOST_CRCINITFlagforSpartan-6devices. AddednewVccoSenseMode(VCCOSENSEMODE)constraint. Constraints Guide 2 www.xilinx.com UG625 (v. 13.3) October 19, 2011 Table of Contents RevisionHistory....................................................................................................2 Chapter 1 Constraint Types.........................................................................................9 AttributesandConstraints....................................................................................9 CPLDFitter...........................................................................................................10 GroupingConstraintsforTiming.......................................................................11 LogicalConstraints..............................................................................................14 PhysicalConstraints.............................................................................................15 MappingDirectives.............................................................................................16 PlacementConstraints.........................................................................................17 RoutingDirectives...............................................................................................19 SynthesisConstraints..........................................................................................20 TimingConstraints..............................................................................................21 ConfigurationConstraints...................................................................................25 Chapter 2 Entry Strategies for Xilinx Constraints...................................................27 ConstraintsEntryMethods..................................................................................27 ConstraintsEntryTable.......................................................................................27 SchematicDesign.................................................................................................30 VHDLAttributes..................................................................................................30 VerilogAttributes.................................................................................................31 UserConstraintsFile(UCF).................................................................................33 UCFandNCFFileSyntax....................................................................................34 PhysicalConstraintsFile(PCF)...........................................................................38 NetlistConstraintsFile(NCF).............................................................................40 ConstraintsEditor................................................................................................40 ISEDesignSuite..................................................................................................42 PlanAhead............................................................................................................42 SettingConstraintsinPACE................................................................................46 PartialDesignPinPreassignment.......................................................................46 FPGAEditor.........................................................................................................48 XSTConstraintFile(XCF)...................................................................................50 ConstraintPriority...............................................................................................50 Chapter 3 Timing Constraint Strategies...................................................................53 BasicConstraintsMethodology..........................................................................53 InputTimingConstraints....................................................................................54 ConstraintsGuide UG625(v. 13.3)October19,2011 www.xilinx.com 3 Register-to-RegisterTimingConstraints............................................................58 OutputTimingConstraints.................................................................................62 ExceptionTimingConstraints.............................................................................66 Chapter 4 Xilinx Constraints.....................................................................................69 ConstraintInformation........................................................................................69 AreaGroup...........................................................................................................70 AsynchronousRegister........................................................................................79 BEL........................................................................................................................81 BlockName..........................................................................................................84 BUFG....................................................................................................................86 ClockDedicatedRoute........................................................................................89 Collapse................................................................................................................91 ComponentGroup...............................................................................................93 ConfigurationMode.............................................................................................94 CoolCLOCK.........................................................................................................97 DataGate..............................................................................................................99 DCICascade.......................................................................................................101 DCIValue...........................................................................................................103 Default................................................................................................................104 DiffTerm............................................................................................................107 DirectedRouting................................................................................................109 Disable................................................................................................................111 Drive...................................................................................................................113 DropSpecifications............................................................................................116 Enable.................................................................................................................117 EnableSuspend..................................................................................................119 Fast......................................................................................................................120 Feedback.............................................................................................................122 File.......................................................................................................................124 Float....................................................................................................................126 FromThruTo......................................................................................................128 FromTo...............................................................................................................130 FSMStyle...........................................................................................................132 HierarchicalBlockName...................................................................................133 HIODELAYGroup.............................................................................................135 HierarchicalLookupTableName.....................................................................136 HSet....................................................................................................................138 HUSet.................................................................................................................139 Constraints Guide 4 www.xilinx.com UG625 (v. 13.3) October 19, 2011 InputBufferDelayValue..................................................................................141 IFDDelayValue.................................................................................................143 InTerm................................................................................................................145 InputRegisters...................................................................................................147 InternalVrefBank..............................................................................................148 IOB......................................................................................................................149 InputOutputBlockDelay.................................................................................152 IODELAYGroup................................................................................................154 InputOutputStandard......................................................................................156 Keep....................................................................................................................159 KeepHierarchy..................................................................................................161 Keeper.................................................................................................................164 Location(LOC)...................................................................................................166 Locate..................................................................................................................169 LockPins............................................................................................................182 LookupTableName...........................................................................................183 Map.....................................................................................................................186 MarkDebug.......................................................................................................187 MaxFanout.........................................................................................................189 MaximumDelay.................................................................................................192 MaximumProductTerms..................................................................................194 MaximumSkew.................................................................................................195 MCBPerformance..............................................................................................197 MIODELAYGroup............................................................................................199 NoDelay.............................................................................................................200 NoReduce..........................................................................................................202 OffsetIn..............................................................................................................204 OffsetOut...........................................................................................................210 OpenDrain.........................................................................................................214 OutTerm.............................................................................................................216 Period..................................................................................................................218 Pin.......................................................................................................................227 PostCRC.............................................................................................................228 PostCRCAction.................................................................................................229 PostCRCFrequency..........................................................................................231 PostCRCINITFlag............................................................................................232 PostCRCSignal.................................................................................................234 PostCRCSource.................................................................................................235 ConstraintsGuide UG625(v. 13.3)October19,2011 www.xilinx.com 5 Priority................................................................................................................236 Prohibit...............................................................................................................237 Pulldown............................................................................................................241 Pullup.................................................................................................................243 PowerMode........................................................................................................245 Registers.............................................................................................................247 RelativeLocation(RLOC)..................................................................................249 RelativeLocationOrigin....................................................................................267 RelativeLocationRange....................................................................................270 SaveNetFlag......................................................................................................273 SchmittTrigger...................................................................................................275 SIMCollisionCheck..........................................................................................277 Slew....................................................................................................................279 Slow....................................................................................................................282 Stepping..............................................................................................................284 Suspend..............................................................................................................285 SystemJitter.......................................................................................................287 Temperature........................................................................................................289 TimingIgnore.....................................................................................................291 TimingGroup.....................................................................................................294 TimingSpecifications........................................................................................301 TimingName......................................................................................................304 TimingNameNet...............................................................................................310 TimingPointSynchronization..........................................................................314 TimingThruPoints............................................................................................317 TimingSpecificationIdentifier.........................................................................321 USet....................................................................................................................326 UseInternalVREF..............................................................................................328 UseLUTNM.......................................................................................................330 UseRelativeLocation........................................................................................332 UseLowSkewLines..........................................................................................335 VCCAUX.............................................................................................................337 VCCAUX_IO......................................................................................................338 Voltage................................................................................................................340 VccoSenseMode(VCCOSENSEMODE).........................................................342 VREF...................................................................................................................342 WireAnd............................................................................................................344 XBLKNM............................................................................................................345 Constraints Guide 6 www.xilinx.com UG625 (v. 13.3) October 19, 2011 Appendix Additional Resources.............................................................................347 ConstraintsGuide UG625(v. 13.3)October19,2011 www.xilinx.com 7 Constraints Guide 8 www.xilinx.com UG625 (v. 13.3) October 19, 2011 Chapter 1 Constraint Types ThischapterdiscussestheconstrainttypesdocumentedinthisGuide. Attributes and Constraints Somedesignersusethetermsattributeandconstraintinterchangeably. Otherdesigners givethemdifferentmeanings. Inaddition,certainlanguageconstructsusetheterms attributeanddirectiveinsimilar,butnotidentical,senses. Xilinx®usesthetermsattributes andconstraintsasdefinedbelow. Attributes Anattributeisapropertyassociatedwithadevicearchitectureprimitivecomponent thatgenerallyaffectsaninstantiatedcomponentfunctionalityorimplementation. Attributesarepassedbymeans: • Genericmaps(VHDL) • Defparamsorinlineparameterpassedwhileinstantiatingtheprimitivecomponent (Verilog) AllattributesaredescribedintheXilinxLibrariesGuidesasapartoftheprimitive componentdescription. Attributes Examples • INITonaLUT4component • CLKFX_DIVIDEonaDCM Implementation Constraints TheConstraintsGuidedocumentsimplementationconstraints. AnimplementationconstraintisaninstructiongiventotheFPGAimplementationtools todirectthemapping,placement,timingorotherguidelinestofollowwhileprocessing anFPGAdesign. ImplementationconstraintsaregenerallyplacedintheUserConstraintsFile(UCF). Theymayalsobeplacedin: • TheHardwareDescriptionLanguage(HDL)code • Asynthesisconstraintsfile. Implementation Constraints Examples • Location(LOC)(placement) • PERIOD(timing) ConstraintsGuide UG625(v. 13.3)October19,2011 www.xilinx.com 9 Chapter 1:Constraint Types CPLD Fitter ThefollowingconstraintsapplytoCPLDdevices: BUFG(CPLD) Collapse(COLLAPSE) CoolCLOCK(COOL_CLK) DataGate(DATA_GATE) Fast(FAST) InputRegisters(INREG) InputOutputStandard(IOSTANDARD) Keep(KEEP) Keeper(KEEPER) Location(LOC) MaximumProductTerms(MAXPT) NoReduce(NOREDUCE) OffsetIn(OFFSETIN) OffsetOut(OFFSETOUT) OpenDrain(OPEN_DRAIN) Period(PERIOD) Prohibit(PROHIBIT) Pullup(PULLUP) PowerMode(PWR_MODE) Registers(REG) SchmittTrigger(SCHMITT_TRIGGER) Slow(SLOW) TimingGroup(TIMEGRP) TimingSpecifications(TIMESPEC) TimingName(TNM) TimingSpecificationIdentifier(TSidentifier) VREF WireAnd(WIREAND) Constraints Guide 10 www.xilinx.com UG625 (v. 13.3) October 19, 2011
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