VLSI Implementation of Digital Fourier Transforms Final Report

95 Pages·2002·4.12 MB·English

YLSI Implementation of Digital Fouricr Transforms

Grant nuke

‘Final Report

A, Despain
© Sequin
6 Thomason
E Weld
5, Lioupis

CS, keray

anst'totion: University ef Califcesis

Approved

wubtie relegess duetrib
The view, opixions. and ga vontained in this repors
fathors an Se construed as ai oftcia: Department of tbe Array 308
Son, poly, cr decwsins, Unless s2 designated by outer ocumentacion,
‘Table of Contents

1. OVERVIEN 1

2 INTRODUCTION &

2
22.

Fast Fourice Transform background 9

DFT Architectures S

9, MODULAR CONSTRUCTION OF DFT PROCESSORS ©

au.
a2,

aa.

Be.

Background 5
‘The Radir2 Cooley-Takey Aigorithm 5

3.2.1, Pipeline Structure 5

B22, Notation 6

23, Derivation of Parallel-Pipeline Structures 8

‘824, Partitions of Derived Structures Mt

3.2.5, Examplcs of Paralle/-Hipeline Structures 11

8126, Benchinarks of the Derived Struatures 14

‘The Radint Cooley Tukey Algorithm 1

2.8.1, Pipeline Structure 15

3.02, Notation 16

43.5, Benchmark of the Radix Structures 16

‘The Use of the Winograd Algorithrn in Pipeline Processors 17
94.1. Background 17

B42, Module Implementations 17

BAL, Base Modules 17
2422, Base 3 Kodule 17
34.23, BageS Medule 19
B42, Base 7 Module 22
3425. Base 1i Module 2
3426, Base SModule 23
BAR, Hose 17 odule 2
8428, Higber Bases 2%
94.29, Proposed FFT Cascade 24
8.42.10, Module Memory Cons 25
4. DIPLEVENTATION TECHNOLOGY 81
4.1, Review of the Charge‘Transter Prineipte St
4.2, Implementation Tradcofls
43, A Technology for VIS ¥T Processors 85
‘6. DESCRIPTION OF INTEGRATED CIRCUITS 37
1. 16Point DFT Processor 87
B.2, System-vide Considerations [77
6.2.1, Bit Skowing 37
5.2.2, Multiplexing of the Real and lmaginery Parts 98
5.8. Root I Cirsuit 98
SA, Barrel suitter 41

55. Tprotator 42

6

8.5.1, Theory of operation 42
58, CORDIC Rotater Chip. 4%

5.6.1, Theory of Operation 44

56.2, Detailed Deseription of Data Path and Contre! 48
5.88, Pertortzence Ztimetion 40
5.4, Toating 51

82, Butherfiy Sirouits SL
S74. Introduction 91
5.72, Preliminary Butterfy Processor 51

5.7.9. Compatiste Butlerfy Processor 52

5.74, Chip Tereriptron 88
575. Performance Btimation 58
2.7.6. Testing 55

6. THEORETICAL WORK 37

6.1.1. Tustifcation 57

6.12, Woot is the fonolute Minimum? 5?
6.18, VISIFanin and Fon-out Considerations 57
6.14, Fast Carey Leckahead 56
8.1.5, Othor Special Adder Cireuits 68
6.1.8. Paralle Versus Casoade Sizuctures 68
6.2. A Broad Survey of Fourier Transtorm Circuits 68
6.2.1. Building blocks 70
6.2.2, The Direct Fourier Transform on One Multiply-hdd Coll 7
5.25, The Direct Fourier Transtorm on 17 Cells 72
0.24. Te Direct Fouriar Transform on N? Celle 72
25, The Fast Fourice Transform on One Procassor 74
28, Tue Cascade Implementation of the Fast Fourier Transform 75
6.2.7. The FFT Network 76

6.2.8, The Perfest-Shuflle Implementation of the FFT 78
6.20, The CCC Networe 80
6.2.10, The Mosh Implementation 81
7. CONCLUSIONS 83
8. REFERENCES 8
Figure & Gveral: Base 3 Zircuis
Figure 8 Fart Half of Bore 8 Bucterty
Figurs 16: Las: Eel? o: Bas

Figure 12: Diede y'2 Grou,
Figure 13: Rect 2 Gir

Laut Bece 7 Bus
der Xi

Fleurs 24: Exchange Cre!
igure 25: Reorder Netwrori for Ba:
Bigare 2: Hage 6 Feo-der Networss
Bigare 27: Hass 27 Reorder Networa

ire 28: P-chan:

figure 31- Power D.ssipation among Various Lechnologies
Rgure $2: 1Gzoint

Figure 23: Block
Figure Se: 18 bit
Figure 3; Fabrieaied kag! 7 chip
Figure 36: Schematic of Barrel Suter
Figure 97; Fabriogled Barre! Shuler Chie

Figure 32: Block

Figure 35: CHPPLAY of Zhernip
Figure 49: Book Biegrsm of CORDIC rotavor
Bygure 41: Fioar Zlea vf CORD)

Rigure 42: Stage 5 of the COXDIC Rotator
Figere 43: 4622 Module

Figure 24 inversion of ay

Figure &: Adder and ROP Control Signals

Figure 48; CiPPICT of CORDIC Ret

Figure 47; 19 #8 Butterfly Teoee:

Figure 48: Febsuaced 4 Bi

Figure 42: Fiourpler of Butterfly Module

‘Rgure 80: Scbematic of Busterdy Modute
Prograrameble Daley

Feneia Comparizoa

5} Desired Traneformacion

Deflaition of Fin } Circuits

Figece $7:
Pigure 85
Byare 33:
Bigure
Figare 61:
Figure 62:
Figure 85:
Bigare 54
Figure 65:
Figure 68:
gure

Figure $4
Figure 65:
Figuee 7:
Figure 71
Figure 72
Figure 7:

‘The FFT network
‘The periect shufiie interconsmetions for N=5
The OCC aetwark for 7726

Tre Mash of 8 processors
2 ecu.s ace" {Gentre: Mutupiy not

Ghossing Sat Remster Leng!
Chom “station aagle
Geocities as 0 Function of Fats, ad Oxeuit Delay
Smear Growie

Deeg-tine performance 3: sae Fourier transform-solving eiveaia