VHDL : Programming By Example

497 Pages·2002·2.368 MB·English

by  Douglas Perry

VHDL:
Programming
by Example
Douglas L. Perry
Fourth Edition
McGraw-Hill
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DOI: 10.1036/0071409548
This Book is Dedicated to
my wife Debbie and my son Brennan
Thank you for your patience and support
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CONTENTS
Foreword xiii
Preface xv
Acknowledgments xviii
Chapter 1 Introduction to VHDL 1
VHDL Terms 2
Describing Hardware in VHDL 3
Entity 3
Architectures 4
Concurrent Signal Assignment 5
Event Scheduling 6
Statement Concurrency 6
Structural Designs 7
Sequential Behavior 8
Process Statements 9
Process Declarative Region 9
Process Statement Part 9
Process Execution 10
Sequential Statements 10
Architecture Selection 11
Configuration Statements 11
Power of Configurations 12
Chapter 2 Behavioral Modeling 15
Introduction to Behavioral Modeling 16
Transport Versus Inertial Delay 20
Inertial Delay 20
Transport Delay 21
Inertial Delay Model 22
Transport Delay Model 23
Simulation Deltas 23
Drivers 27
Driver Creation 27
Bad Multiple Driver Model 28
Generics 29
Block Statements 31
Guarded Blocks 35
vi Contents
Chapter 3 Sequential Processing 39
Process Statement 40
Sensitivity List 40
Process Example 40
Signal Assignment Versus Variable Assignment 42
Incorrect Mux Example 43
Correct Mux Example 45
Sequential Statements 46
IF Statements 47
CASE Statements 48
LOOP Statements 50
NEXT Statement 53
EXIT Statement 54
ASSERT Statement 56
Assertion BNF 57
WAIT Statements 59
WAIT ON Signal 62
WAIT UNTIL Expression 62
WAIT FOR time_expression 62
Multiple WAIT Conditions 63
WAIT Time-Out 64
Sensitivity List Versus WAIT Statement 66
Concurrent Assignment Problem 67
Passive Processes 70
Chapter 4 Data Types 73
Object Types 74
Signal 74
Variables 76
Constants 77
Data Types 78
Scalar Types 79
Composite Types 86
Incomplete Types 98
File Types 102
File Type Caveats 105
Subtypes 105
Chapter 5 Subprograms and Packages 109
Subprograms 110
Function 110
Contents vii
Conversion Functions 113
Resolution Functions 119
Procedures 133
Packages 135
Package Declaration 136
Deferred Constants 136
Subprogram Declaration 137
Package Body 138
Chapter 6 Predefined Attributes 143
Value Kind Attributes 144
Value Type Attributes 144
Value Array Attributes 147
Value Block Attributes 149
Function Kind Attributes 151
Function Type Attributes 151
Function Array Attributes 154
Function Signal Attributes 156
Attributes ’EVENT and ’LAST_VALUE 157
Attribute ’LAST_EVENT 158
Attribute ’ACTIVE and ’LAST_ACTIVE 160
Signal Kind Attributes 160
Attribute ’DELAYED 161
Attribute ’STABLE 164
Attribute ’QUIET 166
Attribute ’TRANSACTION 168
Type Kind Attributes 169
Range Kind Attributes 170
Chapter 7 Configurations 173
Default Configurations 174
Component Configurations 176
Lower-Level Configurations 179
Entity-Architecture Pair Configuration 180
Port Maps 181
Mapping Library Entities 183
Generics in Configurations 185
Generic Value Specification in Architecture 188
Generic Specifications in Configurations 190
Board-Socket-Chip Analogy 195
Block Configurations 199
Architecture Configurations 201
viii Contents
Chapter 8 Advanced Topics 205
Overloading 206
Subprogram Overloading 206
Overloading Operators 210
Aliases 215
Qualified Expressions 215
User-Defined Attributes 218
Generate Statements 220
Irregular Generate Statement 222
TextIO 224
Chapter 9 Synthesis 231
Register Transfer Level Description 232
Constraints 237
Timing Constraints 238
Clock Constraints 238
Attributes 239
Load 240
Drive 240
Arrival Time 240
Technology Libraries 241
Synthesis 243
Translation 243
Boolean Optimization 244
Flattening 245
Factoring 246
Mapping to Gates 247
Chapter 10 VHDL Synthesis 251
Simple Gate—Concurrent Assignment 252
IF Control Flow Statements 253
Case Control Flow Statements 256
Simple Sequential Statements 257
Asynchronous Reset 259
Asynchronous Preset and Clear 261
More Complex Sequential Statements 262
Four-Bit Shifter 264
State Machine Example 266
Contents ix
Chapter 11 High Level Design Flow 273
RTL Simulation 275
VHDL Synthesis 277
Functional Gate-Level Verification 283
Place and Route 284
Post Layout Timing Simulation 286
Static Timing 287
Chapter 12 Top-Level System Design 289
CPU Design 290
Top-Level System Operation 290
Instructions 291
Sample Instruction Representation 292
CPU Top-Level Design 293
Block Copy Operation 299
Chapter 13 CPU: Synthesis Description 303
ALU 306
Comp 309
Control 311
Reg 321
Regarray 322
Shift 324
Trireg 326
Chapter 14 CPU: RTL Simulation 329
Testbenches 330
Kinds of Testbenches 331
Stimulus Only 333
Full Testbench 337
Simulator Specific 340
Hybrid Testbenches 342
Fast Testbench 345
CPU Simulation 349
Chapter 15 CPU Design: Synthesis Results 357