Table Of Content

VHDL MODELING FOR DIGITAL DESIGN SYNTHESIS VHDL MODELING FOR DIGITAL DESIGN SYNTHESIS by Yu-Chin Hsu Kevin F. Tsai Jessie T. Liu Eric S. Lin University of California, Riverside "~. SPRINGER SCIENCE+BUSlNESS MEDIA, LLC ISBN 978-1-4613-5993-7 ISBN 978-1-4615-2343-7 (eBook) DOI 10.1007/978-1-4615-2343-7 Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. (Appendix B.1 and B.2) Reprinted from IEEE Std 1076-1993 IEEE Standard VHDL Reference Manual, CopyrightC 1944 by The Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or Liability resulting from the placement and use in this publication. Information is reprinted with the permission of the IEEE. (Appendix B.3) Reprinted from IEEE Std 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std Jogic_ 1164), CopyrightC 1993 by The Institute of Electrical and Electronics Engineers, Inc. The IEEE disclaims any responsibility or liability resulting from the placement and use in this publication. Information is reprinted with the permission of the IEEE. (Appendix B.4) Reprinted from IEEE Draft Std P1076.3 IEEE Draft Standard VHDL Synthesis Package, Copyrightc 1995 by The Institute of Electrical and Electronics Engineers', Inc. This information represents a portion of the IEEE Draft Standard and is unapproved and subject to change. Use of the information contained in the unapproved draft is at your own risk. The IEEE disclaims any responsibility or liability resulting from the placement and use in this publication. Information is reprinted with the permission of the IEEE. Copyright © 1995 by Springer Science+Business Media New York Third Printing 1998. Originally published by Kluwer Academic Publishers in 1995 Softcover reprint of the hardcover 1s t edition 1995 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Printed on acid-free paper. CONTENTS LIST OF FIGURES xi PREFACE xv 1 INTRODUCTION 1 1.1 Design Process 1 1.2 Levels ofAbstraction 2 1.3 Design Tools 5 1.4 VHSIC Hardware Description Languages 7 1.5 Simulation 10 1.6 Synthesis 11 1.7 Summary 13 2 BASIC STRUCTURES IN VHDL 15 2.1 Entity Declarations 16 2.2 Architectures 19 2.2.1 Behavioral style 21 2.2.2 Dataflow style architecture 24 2.2.3 Structural style architecture 25 2.3 Packages 29 2.4 Configurations 30 2.5 Design Libraries 31 2.6 Summary 33 3 TYPES, OPERATORS AND EXPRESSIONS 35 3.1 Data Objects 35 3.2 Data Types 36 VI VHDL MODELING FOR DIGITAL DESIGN SYNTHESIS 3.2.1 Enumeration Types 37 3.2.2 Integer Types 38 3.2.3 Predefined VHDL Data Types 38 3.2.4 Array Types 39 3.2.5 Record Types 41 3.2.6 STD-LOGIC Data Types 42 3.2.7 SIGNED and UNSIGNED Data Types 43 3.2.8 Subtypes 44 3.3 Operators 44 3.3.1 Logical Operators 45 3.3.2 Relational Operators 45 3.3.3 Adding Operators 46 3.3.4 Sign Operators 47 3.3.5 Multiplying Operators 47 3.4 Operands 47 3.4.1 Literals 48 3.4.2 Identifiers 49 3.4.3 Indexed Names 49 3.4.4 Slice Names and Aliases 50 3.4.5 Attributes Names 50 3.4.6 Aggregates 51 3.4.7 Qualified Expressions 52 3.4.8 Type Conversions 53 3.5 Summary 53 4 SEQUENTIAL STATEMENTS 57 4.1 Variable Assignment Statements 58 4.2 Signal Assignment Statements 59 4.3 IfStatements 62 4.4 Case Statements 63 4.5 Null Statements 65 4.6 Assertion Statements 65 4.7 Loop Statements 66 4.8 Next Statements 69 4.9 Exit Statements 69 4.10 Wait Statements 70 Contents vii 4.11 Procedure Calls 72 4.12 Return Statements 73 4.13 Summary 73 CONCURRENT STATEMENTS 5 75 5.1 Process Statements 76 5.2 Concurrent Signal Assignments 79 5.3 Conditional Signal Assignments 80 5.4 Selected Signal Assignments 82 5.5 Block Statements 83 5.6 Concurrent Procedure Calls 84 5.7 Concurrent Assertion Statements 85 5.8 Summary 85 6 SUBPROGRAMS AND PACKAGES 89 6.1 Subprograms 89 6.2 Packages 95 6.2.1 IEEE Standard Logic Package 98 6.2.2 IEEE Standard Synthesis Packages 100 6.3 Summary 101 7 MODELING AT THE STRUCTURAL LEVEL 105 7.1 Component Declarations 105 7.2 Component Instantiations 106 7.3 Generate Statements 109 7.4 Default Bindings 112 7.5 Configuration Specifications 115 7.6 Configuration Declarations 117 7.7 Modeling a Test Bench 120 7.8 Summary 125 8 MODELING AT THE RT LEVEL 129 8.1 Combinational Logic 130 8.2 Latches 131 8.3 Designs with Two Phase Clocks 134 8.4 Flip-Flops 135 viii VHDL MODELING FOR DIGITAL DESIGN SYNTHESIS 8.5 Synchronous Sets And Resets 137 8.6 Asynchronous Sets And Resets 139 8.7 VHDL Templates for RTL circuits 141 8.8 Registers 144 8.9 Asynchronous Counters 148 8.10 Synchronous Counters 149 8.11 Tri-State Buffers 150 8.12 Busses 153 8.13 Netlist ofRTL Components 155 8.14 Summary 156 9 MODELING AT THE FSMD LEVEL 163 9.1 Moore Machines 164 9.2 Asynchronous Mealy Machines 167 9.3 Synchronous Mealy Machines 171 9.4 Separation ofFSM and Datapath 173 9.5 An FSM with a Datapath (FSMD) 177 9.6 Communicating FSMs 183 9.7 Summary 187 10 MODELING AT THE ALGORITHMIC LEVEL 191 10.1 Process and Architecture 192 10.2 Wait Statements 194 10.3 Synchronous Reset 196 10.4 Asynchronous Reset 200 . 10.5 Registers and Counters 202 10.6 Simple Sequential Circuits 204 10.7 Algorithms 205 10.8 Process Communication 213 10.8.1 Two Way Handshaking Communication 215 10.8.2 One Way Handshaking Communication 217 10.9 Summary 220 11 MEMORIES 227 11.1 Memory Read/Write at the RT Level 229 11.2 Memory Inference at the Algorithmic Level 235 Contents ix 11.3 Summary 238 12 VHDL SYNTHESIS 243 12.1 VHDL Design Descriptions 245 12.1.1 Algorithmic description 246 12.1.2 FSMD description 248 12.1.3 Register transfer description 249 12.1.4 Gate level description 249 12.2 Constraints 250 12.3 Technology Library 250 12.4 Delay Calculation 254 12.5 The Synthesis Tool 256 12.6 Design Space Exploration 258 12.7 Synthesis Directives 265 12.7.1 Synthesis Offand On Directive 265 12.7.2 Asynchronous Set/Reset Directives 267 12.7.3 FUnction Directives 269 12.7.4 State Variable Directives 270 12.7.5 Don't Care Value Directives 272 12.7.6 Register Array Directives 274 12.8 Summary 274 13 WRITING EFFICIENT VHDL DESCRIPTIONS 279 13.1 Software to Hardware Mapping 280 13.2 Variables and Signals 282 13.3 Using minimum bit width 283 13.4 Using effective algorithms 285 13.5 Sharing complex operators using module functions 287 13.6 Specifying don't care conditions 288 13.7 Writing low level code 289 13.8 Summary 290 14 PRACTICING DESIGNS 295 14.1 Bit Clock Generator 295 14.2 Traffic Light Controller 297 14.3 Vending Machine 301 x VHDL MODELING FOR DIGITAL DESIGN SYNTHESIS 14.4 Black Jack Dealer Machine 305 14.4.1 Black Jack Dealer Design 305 14.4.2 Testbench Design 310 14.5 Designing a Stack Computer 312 REFERENCES 323 A RESERVED WORDS 327 B STANDARD LIBRARY PACKAGES 329 B.l The STANDARD Package 329 B.2 The TEXTIO Package 330 B.3 The Standard Logic Package 332 B.4 The Standard Synthesis Packages 337 B.4.1 NUMERIC.J3IT 337 B.4.2 NUMERIC_STD 343 INDEX 353 LIST OF FIGURES Chapter 1 1.1 The Digital Design Process. 3 1.2 The V-chart. 4 1.3 Design tools. 6 1.4 Comparator (a) Entity (b) Behaviorstyle (c) Dataflow style (d) Structural style. 9 1.5 Simulation (a) hardware model (b) simulation waveform. 10 1.6 Synthesis (a) Behavior (b) RTL (c) Logic. 12 Chapter 2 2.1 Entity declarations (a) one-bit adder (b) four-bit adder. 18 2.2 Entity and architectures. 20 2.3 Behavior Model (a) Process model (b) simulation cycle. 23 2.4 StructuralDecomposition (a) ADesign Hierarchy (b) DesignTree. 27 2.5 Design Libraries. 32 Chapter 6 6.1 Behavior Model (a) Resolutionfunction (b) Three hardwareim- plementations. 93 Chapter 7 7.1 Full adder Design (a) Interface (b) Architecture (c) A Design Hierarchy. 107 7.2 Generated Adder (a) for-scheme (b) if-scheme. 111 7.3 A test bench for the full adder. 122 Chapter 8