VHDL Answers to Frequently Asked Questions

400 Pages·1998·14.408 MB·English

by  Ben Cohen (auth.)

VHDLANSWERSTOFREQUENTLY
ASKED QUESTIONS
Second Edition
VHDLANSWERSTOFREQUENTLY
ASKED QUESTIONS
Second Edition
by
Ben Cohen
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
A c.I.P. Catalogue record for this book is available
from the Library of Congress.
ISBN 978-1-4613-7581-4 ISBN 978-1-4615-5641-1 (eBook)
DOI 10.1007/978-1-4615-5641-1
Additional material to this book can be downloaded from http://extras.springer.com.
(I) Reprinted from IEEE Std 1076-1993 JEEE Standard VHDL Language Reference Manual,
Copyright© 1994 by the Institute of Electrical and Electronics Engineers, Inc.
The lE EE disclaims any responsibility or liability resu1ting from the placement (in hard copy or
electronic format) and use in this publication ofthe following documents and packages:
e IEEE Std 1076-1993 JEEE Standard VHDL Language
Reference Manual, Copyright© 1994 by the Institute of Electrical and Electronics
Engineers, Inc.
e Package STANDARD and package TEXTIO from the IEEE Std 1076-1993 JEEE Standard
VHDL Language Reference Manual.
e JEEE Std 1164-1993 JEEE Standard Multivalue Logic System for VHDL Model
loteroperability (Std Logic 1164), Copyright© 1993 by the Institute of Electrical and
Electronics Eogineers, loc.
eJEEE Dmft Standard PI076.3, Version: 2.4, Dated 12 April 1995, Copyright© 1995 by the
Institute of E1ectrical and Electronics Engioeers, loc.. This is an unapproved draft of a
proposed IEEE standard, subject 10 change. Use of information contaioed in the unapproved
draft is at your owo risk.
Information is reprioted with the permission of Ihe IEEE.
Copyright© 1998 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, New York in 1998
Softcover reprint of the hardcover 2nd edition 1998
AII rights reserved. No part of this publication may be reproduced, stored in a retrieval system or
traosmitted in any form or by any means, mechanical, photo-copying, recordiog, or otherwise, without
the prior written permission ofthe publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
I dedicate this book to my wife, Gloria Jean.
Her creative and organizational contributions
proved to be invaluable in the design of the
cover, and the format and title of the book.
Her support throughout this project is deeply
appreciated.
CONTENTS
PREFACE xv
ABOUT THE DISK xix
NOTATION CONVENTIONS
Symbols xxv
Syntactic Description xxvi
ACKNOWLEDGMENTS xxvii
ABOUT THE AUTHOR xxviii
1. LANGUAGE ELEMENTS 1
1.1 WHY VHDL FOR DIGITAL DESIGNS 4
1.2 SALIENT POINTS OF CONCURRENT STATEMENTS 6
1.2.1 Process 6
1.2.2 Concurrent Signal Assigmnent Statements 7
1.2.3 Component Instantiation 8
1.2.4 Concurrent Procedure 8
1.2.5 Generate 9
1.2.6 Concurrent Assertion 9
1.2.7 Block statement 10
1.3 GUARDED SIGNAL ASSIGNMENTS 11
1.4 SIGNALS AND PORTS 17
1.4.1 Disconnecting a Signal 17
1.4.2 Difference between inout and buffor ports 17
1.4.3 Port Association Rules - the Open 20
1.4.4 Type Conversion in Port Associations 22
1.5 CONFIGURATIONS 24
1.5.1 Configuration Requirements 24
1.5.2 Configuration SpecificationiDeclaration 25
1.5.2.1 Configuration Specification 25
1.5.2.2 Configuration Declaration 28
1.5.2.3 Binding with configured components 31
1.5.2.4 Removing a Component from an Architecture through Configuration 31
1.5.3 Configuration Statement for a Specific Generic 32
1.5.4 CONFIGURATION OF GENERATE STATEMENTS 33
1.6 ARITHMETIC ISSUES AND OPERATORS 38
1.6.1 Defining 2'S Complement Value -(2**31) in VHDL 38
1.6.2 Value Casting 39
1.6.3 REMIMOD Difference 40
1.6.4 Non-Associative Operators 41
viii VlIDL Answers to Frequently Asked Questions
1.6.5 Analysis Error with the "&" Operator 42
1.6.6 SpecifYing a Multi-Line String. 43
1.7 PACKAGE STD_LOGIC_1164 43
1.7.1 Differences Std_Logic_1l64'1987 and '1993 43
1.7.2 Accessing Multiple Fields ofStd_Logic_V ector 44
1.7.3 Aliases and Constants 44
1. 7.4 Enumeration Type 46
1.7.4.1 Separate conversion functions. 46
1.7.4.2 Use ofInteger Subtypes 47
1.7.4.3 Use of 'val attributes 47
1. 7.5 Testbench for Demonstration Models 48
1.8 RANGE CONSTRAINT IN TYPE DEFINITION 50
1.9 SHARED VARIABLES 50
2. ARRAYS 55
2.1 ARRAY STRUCTURE REPRESENTATIONS 56
2.1.1 One Dimensional Arrays 56
2.1.2 Multi-Dimentional Arrays 56
2.2 ARRAYS - LEGAL OPERATIONS 58
2.2.1 Overloaded Operators on Arrays 60
2.3 ARRAY SLICES AND RANGES 65
2.4 ARRAY INITIALIZATION 67
2.5 CONSTANT ARRAYS IN CASE 70
2.6 CONSTRAINED AND UNCONSTRAINED ARRAYS 71
2.6.1 Constraining Metllods 72
2.6.2 Allowed Constrained and Unconstrained Objects 73
2.7 MAPPING ARRAYS OF DIFFERENT SIZES 74
2.8 UNCONSTRAINED AGGREGATE WITH "OTHERS " 75
2.9 ILLEGAL ARRAY TYPES 78
2.9.1 UNCONSTRAINED ARRAY OF AN UNCONSTRAINED ARRAY 78
3. DRIVERS 81
3.1 MULTIPLE DRIVERS -CASE 1 82
3.1.1 Std_Logic_V ector Solution 83
3.1.2 Separate Signals Solution 83
3.1.3 Atomicity 84
Table of Contents ix
3.2 MULTIPLE DRIVERS -CASE 2 91
3.3 MULTIPLE DRIVERS ERROR-CASE 3 92
3.4 MULTIPLE DRIVERS ERROR - COMPONENT 93
3.5 CODING STYLE FOR DETECTION OF MULTIPLE DRIVERS 95
4. SUBPROGRAMS 99
4.1 SIDE EFFECTS FROM A PROCEDURE 100
4.1.1 Language View 100
4.1.2 STYLE VIEW 103
4.2 GARBAGE COLLECTION OF DYNAMICALLY CREATED OBJECTS 106
4.3 ACCEPTABLE TYPES IN PARAMETER LISTS FOR FUNCTION CALLS 110
4.4 FILES DECLARATIONS IN PROCEDURES 111
4.5 MULTIPLE ACCESSES OF SAME FILE 113
4.6 FILE ARRAY 114
4.7 CONVERSION FUNCTION FROM INTEGER TO TIME 116
4.8 NORMALIZATION IN SUBPROGRAMS 118
5. PACKAGES 121
5.1 CONVERTING TYPED OBJECTS TO STRINGS 122
5.2 PRINTING OBJECTS FROM VHDL 126
5.2.1 Writing to One file from Multiple Processes 129
5.3 MULTIPLE INPUT SIGNATURE REGISTER (MISR) 130
5.4 DESIGN OF A LINEAR FEEDBACK SHIFT REGISTER (LFSR) 132
5.5 RANDOM NUMBER GENERATION 137
5.6 DEFERRED CONSTANT IN PACKAGE DECLARATION 138
5.7 COMPLEX NUMBERS AND OVERLOADED OPERATORS 138
5.8 IEEE STANDARDS 143
6. MODELS 145
x VHDL Answers to Frequently Asked Questions
6.1 LARGE RAM MODEL FOR SIMULATION. 146
6.1.1 Traditional Memory Modeling 146
6.1.2 Efficiency Memory Modeling 149
6.1.3 Fixed Army Caching 149
6.1.4 Fixed Page Caching 152
6.1.5 Dynamic Page Caching 154
6.1.6 Disk paging with swap files 156
6.1. 7 C Language Interface 157
6.1.8 RAM Testbench and Configurations 157
6.2 ZERO OHM RESISTOR (WIRE, BRIDGE) MODEL 159
6.2.1 Zero Ohm Resistor Model Restrictions 162
6.2.2 Architecture Variation Method for Resistor 163
6.3 ERROR INJECTOR MODEL 163
6.4 TRANSFER GATE (SWITCH) 178
7. SYNTHESIS 183
7.1 SUPPORTEDIUNSUPPORTED CONSTRUCTS FOR SYNTHESIS 184
7.2 SYNTHESIS SENSITMTY RULES 186
7.3 LATCH/REGISTER/COMBINATIONAL LOGIC 186
7.4 LATCH INFERRANCE IN FUNCTIONS 193
7.5 VARIABLE INITIALIZATION AND LIFETIME 193
7.5.1 Variable Initialization in Processes 193
7.5.2 Variable Initialization for Subprograms (Called from Processes) 195
7.6 WAIT STATEMENT 195
7.7 DEFINING SHIFT REGISTERS IN SYNTHESIS 197
7.7.1 Resolution --Code for Shift Register 197
7.8 REGISTER FILE 199
7.8.1 Register File - with signals 199
7.8.2 Register File - with variables 200
7.9 MULTIPLEXER MODEL 202
7.10 DEMULTIPLEXER MODEL 203
7.11 BARREL SHIFTER 205
7.12 USE OF "DON'T CARE" IN CASE STATEMENT 207
7.12.1 Case Statement with No "Don't Care" 208
7.12.2 IF Statement 210
Table of Contents xi
7.12.3 Loop Statement 210
7.12.4 IEEE Std_Synth 211
7.13 PARAMETERIZED PRIORITY ENCODER 212
7.13.1 Straight Encoding Priority Encoder 213
7.13.2 Two level encoding 215
7.14 GENERATING A SYNCHRONOUS PRECHARGE 220
7.15 TECHNOLOGY AND VHDL CODE DESIGN 223
7.15.1 Basic architecture ofa logic cell. 223
7.15.2 Synthesis tool teclmology 226
7.15.3 Supporting component libraries 226
7.16 SYNTHESIZING TRI-STATES 226
7.16.1 Latches in Tri-State Controls 227
7.17 SUBELEMENT ASSOCIATION 230
7.17.1 Subelement Association for Ports 231
7.18 FINITE STATE MACHINE (FSM) 232
7.19 ONE-HOT ENCODING 233
7.20 INSTANTIATING SYNOPSYS® DESIGNWARE COMPONENTS 234
7.21 RESOURCE SHARING 235
7.22 APPLYING DIGITAL DESIGN EXPERIENCES 236
7.23 ADDRESS RANGE IDENTIFICATION VIA INFERRED COMPARATOR 238
7.24 PORT MAPPING TO GROUND OR VCC 239
7.25 BIT REVERSAL 240
7.26 HOW TO DESIGN A TIMER IN VHDL 241
7.27 SPECIFYING A MULTIPLIER 242
7.28 BEHAVIORAL SYNTHESIS 243
8. DESIGN VERIFICATION AND TESTBENCH 245
8.1 VERIFICATION PROCESSES 246
8.2 FUNCTIONAL VERIFICATION 247
8.3 REGRESSION TESTS 250
8.3.1 File Compare Method 250
Xli VHDL Answers to Frequently Asked Questions
8.3.2 Design Verifier MetllOd 251
8.3.3 MISR MetllOd 251
8.3.4 Formal Verification Metllod 252
8.4 FORMAL VERIFICATION 252
8.4.1 How Formal Verification Works 252
8.4.2 How Formal Verification Fits in tlle Design Cycle 253
8.4.3 Formal Verification Advantages 253
8.5 BUS FUNCTIONAL MODEL (BFM) MODELING 254
8.6 APPLICATION OF MISR, RANDOM, LFSR PACKAGES FOR AUTO-
REGRESSION 257
8.7 STRENGTH STRIPPER 267
9. POTPOURRI 269
9.1 METHODS TO ENHANCE SIMULATION SPEED 270
9.1.1 Signals 270
9.1.1.1 Use Signals for Inter-Process Communication Only 271
9.1.1.2 Avoid Signal Reassignment for Same Value 271
9.1.1.3 Avoid Individual Assignment ofIndividual Elements of a Composite 271
9.1.1.4 Reduce Number of Signals 272
9 .1.1.5 Avoid resolved signals 272
9.1.2 Concurrent Statements 273
9.1.2.1 Number ofProcesseslConcurrent Statements 273
9.1.2.2 Concurrent Signal Assignment, Sensitivity list or Wait Statements[6] 273
9.1.2.3 Processes Witll Multiple Clocks 275
9.1.2.4 Disabling Non-Necessary Concurrent Statements 275
9.1.2.5 Avoid Repeated Code or Function Calls 277
9.1.2.6 Avoid Unnecessary Processes 278
9.1.3 Types 278
9.1.4 Constants 279
9.1.5 Files 280
9.1.6 Subprograms 284
9.1.7 Memory 284
9.1.8 Packages 285
9.1.9 VITAL 285
9.2 ACCESSING SIGNALS INTERNAL TO COMPONENTS 285
9.2.1 Global Signal Metllod 285
9.2.2 PORT MetllOd 289
9.3 TRANSFERRING A LINE ONTO A SIGNAL 291
9.4 TYPE DECLARATION IN MULTIPLE PACKAGES 293
9.5 INTERNET -FREQUENTLY ASKED QUESTIONS 294