Description:

As the title says, this presents only the deltas from the previous version of the spec. If you're not already reasonably conversant with VHDL, this won't do a thing for you. But, if you've used VHDL long enough to be utterly maddened by some of its shortcomings, get this one. You're in for some happy surprises. The two biggest changes have to do with generics and with assertions. Since day one, logic designers have treated strongly-typed VHDL as an untyped language. We've had to cast everything to bitvectors, like a PL/I programmer who uses unspec for everything, because of inflexible typing. A FIFO, for example, that handled one data type could never be reused with a different type. You'd have rewrite the entire FIFO, identical in every way, except for the data type. Yuk - better to cast everything to std_logic_vector, reuse the component, and adopt the old C-language slogan: "strong typing is for weak memories." Generic types, more like C++ templates, get past that. Generic subprograms increase reusability, too. If you're new to the concept, it's like passing a function as parameter, but at compile time. In the world VHDL addresses, compile-time binding is just fine. Much has been made of SystemVerilog assertions - and with good reason. They add a huge level of expressiveness to the verification engineer's task, and represented a real advance over what VHDL had. The gap closes with VHDL's integrated PSL. I haven't done a point by point comparison, but SV assertions and PSL appear to have closely comparable feature sets. That includes Verilog's scope-busting ability to reach internal signals deep down in the structure hierarchy, but PSL allows up-level references, too. VHDL 2008 also includes minor features that scratch many itches from the previous standards: ability to use std_logic values as "if" tests without casting to boolean, conditional assignments in sequential blocks, bitwise reduction operators, and fixes to other niggling annoyances that people have been coding around for years. The one thing conspicuous by its absence is mention of what's in the synthesizable subset. Using advanced features in testbenches is nice. But, if you can't put them in the payload logic, they tend to create impedance mismatch where the application plugs into the test harness. Also, one of VHDL's big advantages has been its formally standardized synthesizable subset. That meant you could code for one tool suite and have some assurance that your work would port to other tools, too. Without that kind of contract for reusability, the new features (especially richer generics) will never live up to their promise. This book is just a stopgap, and will become obsolete once complete VHDL references include the new features. Those books aren't out yet, however, and this is. For now, I recommend this highly to anyone who uses or develops VHDL tools. -- wiredweird