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Verilog HDL Design Examples 2 Verilog HDL Design Examples Joseph Cavanagh 3 CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2018 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed on acid-free paper Version Date: 20170918 International Standard Book Number-13: 978-1-138-09995-1 (Hardback) This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. 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Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe. Library of Congress Cataloging-in-Publication Data Names: Cavanagh, Joseph, author. Title: Verilog HDL design examples / Joseph Cavanagh. Description: Boca Raton, FL : CRC Press, 2017. | Includes index. 4 Identifiers: LCCN 2017022734| ISBN 9781138099951 (hardback : acid-free paper) | ISBN 9781315103846 (ebook) Subjects: LCSH: Digital electronics--Computer-aided design. | Logic design. | Verilog (Computer hardware description language) Classification: LCC TK7868.D5 C3948 2017 | DDC 621.381--dc23 LC record available at https://lccn.loc.gov/2017022734 Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com 5 CONTENTS Preface Chapter 1 Introduction to Logic Design Using Verilog HDL 1.1 Logic Elements 1.1.1 Comments 1.1.2 Logic Gates 1.1.3 Logic Macro Functions 1.1.4 Procedural Flow Control 1.1.5 Net Data Types 1.1.6 Register Data Types 1.2 Expressions 1.2.1 Operands 1.2.2 Operators 1.3 Modules and Ports 1.3.1 Designing a Test Bench for Simulation 1.4 Built-In Primitives 1.4.1 Built-In Primitive Design Examples 1.5 User-Defined Primitives 1.5.1 Defining a User-Defined Primitive 1.5.2 Combinational User-Defined Primitives 1.5.3 Sequential User-Defined Primitives 1.6 Dataflow Modeling 1.6.1 Continuous Assignment 1.6.2 Reduction Operators 1.6.3 Conditional Operator 1.6.4 Relational Operators 1.6.5 Logical Operators 1.6.6 Bitwise Operators 1.6.7 Shift Operators 1.7 Behavioral Modeling 1.7.1 Initial Statement 1.7.2 Always Statement 6 1.7.3 Intrastatement Delay 1.7.4 Interstatement Delay 1.7.5 Blocking Assignments 1.7.6 Nonblocking Assignments 1.7.7 Conditional Statements 1.7.8 Case Statement 1.7.9 Loop Statements 1.7.10Logical, Algebraic, and Rotate Shift Operations 1.8 Structural Modeling 1.8.1 Module Instantiation 1.8.2 Ports 1.8.3 Design Examples 1.9 Tasks and Functions 1.9.1 Task Declaration 1.9.2 Task Invocation 1.9.3 Function Declaration 1.9.4 Function Invocation 1.10 Problems Chapter 2 Combinational Logic Design Using Verilog HDL 2.1 Number Systems 2.1.1 Binary Number System 2.1.2 Octal Number System 2.1.3 Decimal Number System 2.1.4 Hexadecimal Number System 2.2 Boolean Algebra 2.2.1 Axioms 2.2.2 Theorems 2.2.3 Other Terms for Boolean Algebra 2.3 Logic Equations 2.4 Multiplexers 2.5 Comparators 2.6 Programmable Logic Devices 2.6.1 Programmable Read-Only Memories 2.6.2 Programmable Array Logic 2.6.3 Programmable Logic Array 2.7 Additional Design Examples 7 2.8 Problems Chapter 3 Sequential Logic Design Using Verilog HDL 3.1 Introduction 3.1.1 Definition of a Sequential Machine 3.2 Synchronous Sequential Machines 3.2.1 Synthesis Procedure 3.2.2 Equivalent States 3.2.4 Mealy Machines 3.2.5 Synchronous Registers 3.2.6 Synchronous Counters 3.3 Asynchronous Sequential Machines 3.3.1 Synthesis Procedure 3.3.2 Hazards 3.3.3 Oscillations 3.3.4 Races 3.3.5 Design Examples of Asynchronous Sequential Machines 3.4 Pulse-Mode Asynchronous Sequential Machines 3.4.1 Synthesis Procedure 3.4.2 SR Latches with D Flip-Flops as Storage Elements 3.4.3 T Flip-Flops as Storage Elements 3.5 Problems Chapter 4 Computer Arithmetic Design Using Verilog HDL 4.1 Introduction 4.2 Fixed-Point Addition 4.2.1 Full Adder 4.2.2 Three-Bit Adder 4.2.3 Four-Bit Ripple-Carry Adder 4.2.4 Carry Lookahead Adder 4.3 Fixed-Point Subtraction 4.3.1 Four-Bit Ripple Subtractor 4.3.2 Eight-Bit Subtractor 4.3.3 Four-Bit Dataflow Adder/Subtractor 4.3.4 Eight-Bit Behavioral Adder/Subtractor 4.4 Fixed-Point Multiplication 4.4.1 Behavioral Four-Bit Multiplier 8 4.4.2 Three-Bit Array Multiplier 4.4.3 Four-Bit Dataflow Multiplication Using the Multiply Operator 4.5 Fixed-Point Division 4.6 Arithmetic and Logic Unit 4.7 Decimal Addition 4.7.1 Decimal Addition with Sum Correction 4.7.2 Decimal Addition Using Multiplexers for Sum Correction 4.8 Decimal Subtraction 4.8.1 Decimal Subtraction Using Full Adders and Built-In Primitives for Four Bits 4.8.2 Decimal/Binary Subtraction Using Full Adders and Built- In Primitives for Eight Bits 4.8.3 Eight-Bit Decimal Subtraction Unit with Built-In Primitives and Full Adders Designed Using Behavioral Modeling 4.9 Decimal Multiplication 4.10 Decimal Division 4.11 Floating-Point Addition 4.12 Floating-Point Subtraction 4.12.1True Addition and True Subtraction 4.13 Floating-Point Multiplication 4.14 Floating-Point Division 4.15 Problems Appendix AEvent Queue Appendix BVerilog Project Procedure Appendix CAnswers to Select Problems Index 9 To David Dutton CEO, Silvaco, Inc. for generously providing the SILOS Simulation Environment software for all of my books that use Verilog HDL and for his continued support 10