Verilog Digital Computer Design: Algorithms Into Hardware

637 Pages·1998·8.61 MB·English

by  Mark Gordon Arnold

Verilog Digital
Computer Design
Algorithms into
Hardware
ISBN 0-13-639253-9
91 0111161111 1
Verilog Digital
Computer Design
Algorithms into Hardware
Mark Gordon Arnold
University of Wyoming
Prentice Hall PTR
Upper Saddle River, NJ 07458
http://www.phptr.com
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Table of Contents
Page
Preface.............................................................................................................. xxvii
Acknowledgements ......................................... xxix
1. WHY VERILOG COMPUTER DESIGN? . .................................. 1
1.1 What is computer design? ................... .. 1.......................
1.1.1 General-purpose computers ............. ................................ 1
1.1.2 Special-purpose computers......................................................................1
1.2 A brief history of computer/digital technology ............................................ 2
1.3 Translating algorithms into hardware ............................................ 3
1.4 Hardware description languages ............................................ 4
1.5 Typography ............................................. 5
1.6 Assumed background ............................................. 6
1.7 Conclusion ............................................. 6
I . T-VlJVF-.-T-C- N-TlN T A -&--4 - --------------------------.......... 7
2.1 What is an ASM chart? ....... ............................. . . .. 7
2.1.1 ASM chart commands ........................................ 9
2.1.1.1 Asserting a one-bit signal ........................................ 9
2.1.1.2 Outputting a multi-bit command........................................................ 10
marketing, and resale. 2.1.1.3 Register transfer ................ . . 11
2.1.2 Decisions inASM charts . . . ..................................... 12
6-7141, 2.1.2.1 Relations ......................................... 13
2.1.2.2 External status .. ...................................... 14
2.1.3 Inputs and outputs of an ASM ........................................ 15
2.1.3.1 ASM inputs ......................................... 16
2.1.3.1.1 Externalstatusinputs ........................................ 16
2.1.3.1.2 External data inputs .......... .............................. 16
2.1.3.2 ASM outputs ................ .. ...................... 17
2.1.3.2.1 External command outputs ........................................ 18
2.1.3.2.2 External data outputs ........................................ 18
2.1.4 Goto-less style ...... ................... . 18
2.1.5 Top-down design . . ...................................... 19
2.1.5.1 Pure behavioral .. ...................................... 19
2.1.5.2 Mixed ......................................... 20
2.1.5.3 Pure structure ................ .. ...................... 22
2.1.6 Design automation ........................................ 22
2.2 Pure behavioral example . . . . .................................... 22
2.2.1 A push button interface .................. ...................... 24
2.2.2 An ASM incorporating software dependencies ...................................... 26
2.2.3 Eliminating state TEST ......... ............................... 29
2.2.4 Eliminating state INIT . ....................................... 31
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3.
2.2.5 Saving the quotient ............................................... 33
2.2.6 Variations within the loop ............................................... 34
2.2.7 Eliminate state ZEROR3 .............. ................................. 38
2.3 Mixed examples ............................................... . 40
2.3.1 First example ............................................... 41
3.
2.3.2 Second example ............................................... 45
2.3.3 Third example ............................................... 46
2.3.4 Methodical versus central ALU architectures ........................................ 48
2.4 Pure structural example ........... .................................... 49
2.4.1 First example ............................................... 49
2.4.2 Second example ............................................... 51 3.8
3.8
2.5 Hierarchical design ......... ....................................... 52
3.
2.5.1 How pure is "pure"? ............................................... 56
3.
2.5.2 Hierarchy in the first example ..................... .......................... 57
2.6 Conclusion ............................................... 59
2.7 Further Reading ................................................ 59
2.8 Exercises ............................................... 60
3. VERILOG HARDWARE DESCRIPTION LANGUAGE ..... 64
3.1 Simulation versus synthesis . . ............................................. 64
3.2 Verilog versus VHDL . . . ............................................ 65
3.3 Role of test code ............................................... 65
3.4 Behavioral features of Verilog . . ............................................. 66
3.4.1 Variable declaration ..................... .......................... 67
3.9
3.4.2 Statements legal in behavioral Verilog . ................................6. 8
3.
3.4.3 Expressions .. ............................................. 69
3.4.4 Blocks ............................................... 70
3.4.5 Constants ............................................... 73
3.
3.4.6 Macros, include files and comments ............................................... 73
3.5 Structural features of Verilog . . ............................................. 74
3.5.1 Instantiating multiple gates .................... ........................... 75
3.1'
3.5.2 Comparison with behavioral code ............................................... 76
3.
3.5.3 Interconnection errors: four-valued logic . ..............................7.7
3.
3.5.3.1 High impedance ............................................... 77
3.
3.5.3.2 Unknown value ............................................... 78
3.
3.5.3.3 Use in behavioral code ............... ................................ 78
3.
3.6 $time ................................................ 81
3.
3.6.1 Multiple blocks ................................................ 81
3
3.6.2 Sequence versus $time .............................................. 82
3.
3.6.3 Scheduling processes and deadlock . ..................................8. 2
3.
3.7 Time control ............................................... 83
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........................... 33 3.7.1 # time control. . ........................................................................................ 83
........................... 34 3.7.1.1 Using # in test code .................................................... 84
.......................... 38 3.7.1.2 Modeling combinational logic with # ................................................ 85
........................... 40 3.7.1.3 Generating the system clock with # for simulation .......................... 87
.......................... 41 3.7.1.4 Ordering processes without advancing $time ............. ....................... 87
. ................. 45 3.7.2 @t ime control .................................................... 88
........................... 46 3.7.2.1 Efficient behavioral modeling of combinational logic with @ ... 89
.......................... 48 3.7.2.2 Modeling synchronous registers .................................................... 90
.......................... 49 3.7.2.3 Modeling synchronous logic controllers. . 91
.......................... 49 3.7.2.4 @ for debugging display.................................................................... 92
.......................... 51 3.7.3 wait . . . . ................................................ 93
.......................... 52 3.8 Assignment with time control .................................................... 94
........................... 56 3.8.1 Blocking procedural assignment ................................................ .... 95
.......................... 57 3.8.2 Non-blocking procedural assignment . . .................................................... 95
........................... 59 3.8.2.1 Problem with <= for RTN for simulation .......................................... 96
........................... 59 3.8.2.2 Proper use of <= for RTN in simulation ............................................ 98
.......................... 60 3.8.2.3 Translating goto-less ASMs to behavioral Verilog ......... ................... 99
3.8.2.3.1 Implicit versus explicit style........................................................ 99
,.....64 3.8.2.3.2 Identifying the infinite loop .100
...................................................... 664.4.. 3.8.2.3.3 Recognizing if else .101
3.8.2.3.4 Recognizing a single alternative. ...................................... 103
...-..-..,.,..,..,.,..-..,..-..-...,.,..6. 655 3.8.2.3.5 Recognizing while loops .104
........................... 66 3.8.2.3.6 Recognizing forever .106
3.8.2.3.7 Translating into an if at the bottom of forever .108
---......... 67
........... 68 3.9 Tasks and functions . . . . ..................................... 109
...........................6 9 3.9.1 Tasks .......................................... . 109
............................ 70 3.9.1.1 Example task .......................................... 110
.......................... 73 3.9.1.2 enternewstate task ......................................... 112
3.9.2 Functions ..... ...................................... 114
.. ......... 73
.......................... 74 3.9.2.1 Realfunction example ......................................... 115
3.9.2.2 Using a function to model combinational logic ................................ 115
7----.11,11.11.....1 .. 75
.......................... 76 3.10 Structural Verilog, modules and ports ......................................... 117
........................... 77 3.10.1 input ports . . . . 118
......................... 77 3.10.2 output ports . . . . 119
...........................7 8 3.10.3 inout ports . . . . 119
3.10.4 Historical analogy: pins versus ports ...................................... 119
---........ 78
--........ ......... 81 3.10.5 Example of a module defined with a behavioral instance .... 121
. ......... 81 3.10.6 Example of a module defined with a structural instance .... 123
........................... 82 3.10.7 More examples of behavioral and structural instances .... 123
...........................8 2 3.10.8 Hierarchical names . . . . 125
........................... 83 3.10.9 Data structures . . . .126
3.10.10 Parameters .. 128
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3.11 Conclusion ...................................................
129
3.12 Further reading ...................................................
130
3.13 Exercises ...................................................
131
4. THREE STAGES FOR VERILOG DESIGN ................................................... 134
4.1 Pure behavioral examples . . . ................................................1 34
4.1.1 Four-state division machine....................................................................
134
4.1.1.1 Overview of the source code ...................................................
135
4.1.1.2 Details on slowdivision-system ................................................... 137
4.1.2 Verilog catches the error ............................................ 140
4.1.3 Importance of test code ....................... ............................ 141
4.1.4 Additional pure behavioral examples . ................................1..4 3
4.1.5 Pure behavioral stage of the two-state division machine . .................1..4 8
4.2 Mixed stage of the two-state division machine ............................................ 150
4.2.1 Building block devices ...................................................
150
4.2.1.1 enabled register portlist ................ .... ............ .... 51
4.2.1.2 counter-register portlist .151 6.1
4.2.1.3 alul8l portlist .152 6.2
4.2.1.4 comparator portlist .153
6.3
4.2.1.5 mux2 portlist .153
6.
4.2.2 Mixed stage ...............................................
44..22..34 CAorcnhtriotellcetru rfeo rf othr et hdei vdiisvioisni omn amchacinhein..e.. ................................................................................................... 115544 66..
4.3 Pure structural stage of the two state division machine ................................ 115671 66..
44..33..12 Tnehxe t-psutraet esjltrougcitcu rmalo cdounletr oller ................................................................................... .. 116622 66..
4.3.3 stategen function ................................................
4.3.4 Testing state-gen ............................................... 163 6.
4.3.5 It seems to work ............................................... 165 6.
4.4 Hierarchical refinement of the controller . . ............................................. 116667 66..
4.4.1 A logic equation approach......................................................................
4.4.2 At last: a netlist ............................................... 167 6.
168 6.
4.544 ..44..34C onRPcoelussset-itostiynnn g.t htehsei sp rsei.smeunlta stitoant.e .............................................................. .......................................................... .. ............. 111777602 666..
4.6 Exercises . . . ............................................ 176 6
6
5. ADVANCED ASM TECHNIQUES ............................................... 177 6
5.1 Moore versus Mealy ...............................................
177
5.1.1 Silly example of behavioral Mealy machine .......................................... 178
5.1.2 Silly example of mixed Mealy machine ............................................... 179
5.1.3 Silly example of structural Mealy machine ............................................ 180 6.6
6.7
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............................. 129
5.2 Mealy version of the division machine .................................................. 181
............................ 130
5.2.1 Eliminating state INIT again ...................... ............................ 181
............................ 131 5.2.2 Merging states COMPUTEI and COMPUTE2 ...................................... 183
5.2.3 Conditionally loading r2 .................................................. 184
............................ 134
5.2.4 Asserting READY early .................................................. 185
............................ 134
5.3 Translating Mealy ASMs into behavioral Verilog ........................................ 186
............................ 134 5.4 Translating complex (goto) ASMs into behavioral Verilog . ...................1. 88
............................. 135 5.4.1 Bottom testing loop .................................................. 189
............................ 137 5.4.2 Time control within a decision .................................................. 191
............................. 140 r 5.4.3 Arbitrary gotos .................................................. 194
........................... 141
5.5 Translating conditional command signals into Verilog ........... ..................... 194
............................. 143
5.6 Single-state Mealy ASMs .................................................. 196
ae .......... 148 5.7 Conclusion .................................................. 197
........................... 150
............................ 150 6. DESIGNING FOR SPEED AND COST .................................................. 198
........................... 151
6.1 Propagation delay. . ........................................................................................ 199
., ........... 151
6.2 Factors that determine clock frequency . . ................................................ 199
. .......... 152 6.3 Example of netlist propagation delay .................................................. 200
. 153 6.3.1 A priori worst case timing analysis .................................................. 202
. 153 6.3.2 Simulation timing analysis ........................................... 204
. 154 6.3.3 Hazards ................................................... 205
. 154
6.3.4 Advanced gate-level modeling ........................................ 207
. 157
6.4 Abstracting propagation delay . . . ............................................2..0. 9
. 161 6.4.1 Inadequate models for propagation delay .............................................. 209
. 162 6.4.2 Event variables in Verilog ............................................ 212
. 162 6.4.3 The disable statement .................................................. 213
. 163
6.4.4 A clock with a PERIOD parameter .................................................. 215
. 165
6.4.5 Propagation delay in the division machine . ............................2..1 5
............................ 166
6.5 Single cycle, multi-cycle and pipeline . . . ....................................2..1..7.......
. .......... 167 6.5.1 Quadratic polynomial evaluator example . .............................2..1 8
........................... 167
6.5.2 Behavioral single cycle .................................................. 219
............................ 168
6.5.3 Behavioral multi-cycle .................................................. 224
............................ 170
6.5.4 First attempt at pipelining ............................................ 226
........................... 172
6.5.5 Pipelining the ma ................................................... 229
............................ 176
6.5.6 Flushing the pipeline .................................................. 231
........................... 176
6.5.7 Filling the pipeline.................................................................................. 231
6.5.8 Architectures for the quadratic evaluator . ..............................2. 35
........................... 177
6.5.8.1 Single-cycle architecture .................................................. 235
........................... 177
6.5.8.2 Multi-cycle architecture ................ .................................. 238
........................... 178
6.5.8.3 Pipelined architecture .................................................. 241
............................ 179
6.6 Conclusion . . . . .............................................. 245
............................ 180
6.7 Further reading . .................................................. 247
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6.8 Exercises .247
7. ONE HOT DESIGNS ... 249
7.1 Moore ASM to one hot .. . 249 8
7.1.1 Rectangle/flip flop .. 249
7.1.2 Arrow/wire .. 250
7.1.3 Joining together/OR gate .. 250
7.1.4 Decision/demux .. 250
7.1.5 Summary of the one hot method .. 250
7.1.6 First example .. 252
7.2 Verilog to one hot .. . 255
7.2.1 Continuous assignment .. 255
7.2.2 One hot using continuous assignment .. 258
7.2.2.1 One hot with if else . 258
7.2.2.2 One hot with if . 263
7.2.2.3 One hot with while . 264
7.3 Mealy commands in a one hot machine .. . 266
7.4 Moore command signals with Mealy <= .. . 266
7.4.1 Example to illustrate the technique .. 266
7.4.2 Pure behavioral two-state division example .. 270
7.4.3 Mixed two-state division example .. 271
7.5 Bottom testing loops with disable inside forever .. . 273 8.
7.6 Conclusion .. . 275
7.7 Further reading .. . 275
7.8 Exercises .. . 276
8. GENERAL-PURPOSE COMPUTERS . 277
8.1 Introduction and history .. . . 277
8.2 Structure of the machine . 279
8.2.1 CPU, peripheral and memory . 280 8.
8.2.2 Memory: data and the stored program .. . 280
8.2.2.1 Unidirectional buses versus a bidirectional bus . . 281
8.2.2.2 Deterministic versus non-deterministic access time . . 282
8.2.2.3 Synchronous versus asynchronous memory . . 282
8.2.2.3.1 Synchronous memory.................................................................. 282 8.
8.2.2.3.2 Asynchronous memory . 285 8.
8.2.2.4 Static versus dynamic memory .. 286 8.
8.2.2.5 Volatile versus non-volatile .. 286
8.2.3 History of memory technology .. . 286 9. PD]
8.3 Behavioral fetch/execute .. . . 290 9
8.3.1 Limited instruction set .. . 291 9
8.3.1.1 The PDP-8 .. 291
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