Verilog — 2001: A Guide to the New Features of the Verilog® Hardware Description Language

140 Pages·2002·13.301 MB·

by  Stuart Sutherland (auth.)

Verilog-2001
A Guide to the New Features of the
Verilog@ Hardware Description Language
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
V erilog- 2001
A Guide ta the New Features of the
Verilo~ Hardware Description Language
Stuart Sutherland
Sutherland HDL, Inc.
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
ISBN 978-1-4613-5691-2 ISBN 978-1-4615-1713-9 (eBook)
DOI 10.1007/978-1-4615-1713-9
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright © 2002 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2002
Softcover reprint ofthe hardcover Ist edition 2002
AU rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo
copying, recording, or otherwise, without the prior written permission of the
publisher. Springer Science+Business Media, LLC.
Verilog is a registered trademark of Cadence Design Systems, Inc.
Appendix A excerpts are reprinted with permission from the IEEE Std. 1364-2001
IEEE Standard for the Verilog® Hardware Description Language.ISBN 978-1-4613
-5691-2 .Copyright 2001 by the Institute of Electrical and Electronics Engineers,
Inc. (IEEE). The IEEE disclaims any responsibility or liability resulting from the
placement and use in this work.
Printed on acid-free paper.
Dedication
To my wonderful wife, LeeAnn,
and my children: Ammon, Tamara,
Hannah, Seth and Samuel
Table ofC ontents
Foreword, by Phil Moorby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1
Introduction ................................................. 3
What's new in Verilog-2001 .................................... 7
1. Combined port and data type declarations ...................... 8
2. ANSI C style module declarations ........................... 10
3. Module port parameter lists ................................ 12
4. ANSI C style UDP declarations ............................. 14
5. Variable initial value at declaration .......................... 16
6. ANSI C style task/function declarations. . . . . . . . . . . . . . . . . . . . . .. 18
7. Automatic (re-entrant) tasks ... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
8. Automatic (recursive) functions ............................. 22
9. Constant functions ....................................... 24
10. Comma separated sensitivity lists. . . . . . . . . . . . . . . . . . . . . . . . . . .. 26
11. Combinational logic sensitivity lists. . . . . . . . . . . . . . . . . . . . . . . . .. 28
12. Implicit nets for continuous assignments. . . . . . . . . . . . . . . . . . . . .. 32
13. Disabling implicit net declarations . . . . . . . . . . . . . . . . . . . . . . . . . .. 34
14. Variable vector part selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
15. Multidimensional arrays .................................. , 38
16. Arrays of net and real data types ............................ 40
17. Array bit and part selects .................................. 41
18. Signed reg, net and port declarations ......................... 42
19. Signed based integer numbers .............................. 44
20. Signed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 46
21. Sign conversion system functions ........................... 48
22. Arithmetic shift operators ................................. , 50
23. Assignment width extension past 32 bits ...................... 52
24. Power operator .......................................... 54
25. Attributes .............................................. 56
26. Sized and typed parameter constants ......................... 59
27. Explicit in-line parameter redefinition ........................ 62
28. Fixed local parameters .................................... 64
29. Standard random number generator .......................... 66
30. Extended number of open files . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 67
31. Enhanced file 110 ........................................ 70
32. String read and write system tasks ........................... 76
33. Enhanced invocation option testing .......................... 78
34. Enhanced conditional compilation . . . . . . . . . . . . . . . . . . . . . . . . . .. 80
35. Source file and line compiler directive. . . . . . . . . . . . . . . . . . . . . . .. 82
36. Generate blocks ......................................... 84
37. Configurations .......................................... 90
38. On-detect pulse error propagation ........................... 94
39. Negative pulse detection .................................. , 96
40. Enhanced input timing checks .............................. 98
41. Negative input timing constraints. . . . . . . . . . . . . . . . . . . . . . . . . .. 100
42. Enhanced SDF file support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 102
43. Extended VCD files ..................................... 104
44. Enhanced PLA system tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 106
45. Enhanced Verilog PLI support. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 107
Appendix A: Verilog-2001 formal definition. . . . . . . . . . . . . . . . . . . . .. 109
Appendix B: Verilog-2001 reserved words ....................... 131
Index ..................................................... 133
Acknowledgments
I would like to express my gratitude to all those who have helped with this book. A
number of true Verilog experts have taken the time to review all or part of the text,
and provide invaluable feedback on how to make the book useful and accurate. Thank
you Stefen Boyd of Boyd Technology, Shalom Bresticker of Motorola Semiconduc
tor Israel, Ted Elkind of Cadence Design Systems, Adam Krolnik of LSI Logic,
Roger Lutz of Model Technology, Mike McNamara of Verisity DeSign, Dhiraj Raj
of Synopsys and Chris Spear of Synopsys, for taking the time to critique this book
and provide great suggestions.
I would also like to express my appreciation to Phil Moorby of Co-design Automa
tion, Inc., for writing the foreword. Phil created the original Verilog language in 1984.
The IEEE 1364 Verilog Standard Working Group deserves special acknowledgement
for their efforts in defining the Verilog-2001 standard. Following are the primary con
tributors to the creation of the Verilog-2001 standard: Maqsoodul (Maq) Mannan
(chair), Lynn Horobin (secretary), ~urt Baty, Stefen Boyd, Leigh Brady, Shalom
Bresticker, Paul Colwill, Cliff Cummings, Debi Dalio, Charles Dawson, Tom
Dewey, Ted Elkind, Tom Fitzpatrick, Naveen Gupta, Prabhakaran Krishnamur
thy, Adam Krolnik, Andrew Lynch, James Markevitch, Mike McNamara, Steve
Meyer, Anders Nordstrom, Karen Pieper, Girish Rao, David Roberts, Marek
Ryniejski, Lukasz Senator, Steven Sharp, Chris Spear, Stuart Sutherland, Yatin
Trivedi, and Steve Wadsworth.
A special thank you goes to my wife, LeeAnn, for painstakingly wading through all
the hardware engineering jargon in order to review the grammar, punctuation and
sp~lling of the book (I'm sure I managed to insert a few more errors after her review).
Finally, thank you Carl Harris and your staff at Kluwer Academic Publishers for
your help with the complex process of bringing this book from concept to print.
Stuart Sutherland
About the Author
Mr. Stuart Sutherland is a member of the IEEE Verilog standards
committee, where he serves as chair of the Verilog PLI task force
and technical editor for the PLI sections of the IEEE Verilog stan
dard. He is also a member of the Accellera Verilog++ working
group, which is defining the next generation of the Verilog HDL.
Mr. Sutherland also serves as the program committee chair for the
annual International HDL Conference.
Mr. Sutherland has more than 17 years of experience in hardware design and over 13
years of experience with Verilog. He is the founder of Sutherland HDL Inc., located
in Portland Oregon. Sutherland HDL provides expert Verilog HDL and Verilog PLI
design services, including training, modeling, design verification and software tool
evaluation. Verilog training is one of the specialties of Sutherland HDL. Prior to
founding Sutherland HDL in 1992, Mr. Sutherland was employed as an engineer at
Sanders Display Products Division in New Hampshire, where he worked on high
speed graphics systems for the defense industry. In 1988, he became a senior applica
tions engineer for Gateway Design Automation, the founding company of Verilog. At
Gateway, which was acquired by Cadence Design Systems in 1989, Mr. Sutherland
specialized in training and support for logic simulation, timing analysis, fault simula
tion, and the Verilog PLI. Mr. Sutherland has also worked closely with several EDA
vendors to specify, test and bring to market Verilog simulation products.
Mr. Sutherland holds a Bachelor of Science in Computer Science, with an emphasis in
Electronic Engineering Technology, from Weber State University (Ogden, Utah) and
Franklin Pierce College (Nashua, New Hampshire). He has taught Verilog engineer
ing courses at the University of California, Santa Cruz (Santa Clara extension), and
has authored the popular "Verilog HDL Quick Reference Guide" and "Verilog PLI
Quick Reference Guide", as well as the authoritative 800 page "The Verilog PLI
Handbook". He has presented tutorials and papers at the International Verilog Confer
ence and at the International Cadence Users' Group Conference, and has won awards
for best speaker and best tutorial.
visit the author's web page at www.sutherland-hdl.com
3
Introduction
The IEEE Std. 1364-2001, nicknamed "Verilog-2001", is the latest update to the Ver
Hog Hardware Description Language and Verilog Programming Language Interface.
This new Verilog standard adds several significant enhancements to the previous gen
eration of Verilog, the IEEE std. 1364-1995, often called "Verilog-1995". This book
presents 45 key enhancements contained in Verilog-2001 standard. These enhance
ments are essential for both those creating Verilog HDL models and those verifying
model functionality. All of the "top-five" enhancement requests for Verilog-1995
have been incorporated in Verilog-2001. The "top-five" requests are from a survey
conducted at the International HDL Conference held in 1996. The requests were: a
Verilog generate, multi-dimensional arrays, better file 110, re-entrant tasks, and
design configuration control.
The purpose of this book is to show what is new in the Verilog-2001 language. It is
assumed that the reader is already familiar with using Verilog. This book supplements
other excellent books on how to use the Verilog language, such as "Verilog Quick
start: A Practical Guide to Simulation and Synthesis, 2nd Edition", by James Lee
(Kluwer Academic Publishers, ISBN 0-7923-8515-2) and "The Verilog Hardware
Description Language, 4th edition", by Donald Thomas and Philip Moorby (Kluwer
Academic Publishers (ISBN: 0-7923-8166-1).
Caveat: This book does not attempt to convey the full IEEE standard for each
enhancement added in Verilog-2001. While the author has worked diligently to
ensure that this book is accurate, the descriptions of the new features in Verilog-2001
are based on the author's understanding. The final authority is the IEEE 1364-2001
Verilog standard, along with any clarifications approved by the IEEE 1364 Verilog
Standards Group.
Why a Verilog-2001 Standard?
The Verilog Hardware Description Language was first created in 1984. The type of
hardware being designed at that time was primarily full custom ICs, low-speed and
S. Sutherland, Verilog - 2001
© Springer Science+Business Media New York 2002