Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits

89 Pages·2013·3.159 MB·English

by  Martin Wirnshofer

Springer Series in Advanced Microelectronics
Volume 41
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Martin Wirnshofer
Variation-Aware
Adaptive Voltage
Scaling for Digital
CMOS Circuits
MartinWirnshofer
ElectricalEngineering
TechnischeUniversitätMünchen
Munich,Germany
ISSN1437-0387 SpringerSeriesinAdvancedMicroelectronics
ISBN978-94-007-6195-7 ISBN978-94-007-6196-4(eBook)
DOI10.1007/978-94-007-6196-4
SpringerDordrechtHeidelbergNewYorkLondon
LibraryofCongressControlNumber:2013932641
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Preface
Increasingperformancedemandsintoday’sintegratedcircuits(ICs),togetherwith
limitedenergybudgets,forceICdesignerstothinkaboutnewwaysofsavingpower.
One innovative way of doing so is presented in this work. The newly developed
AdaptiveVoltageScaling(AVS)schemetunesthesupplyvoltageofdigitalcircuits
according to the present Process, Voltage and Temperature variations as well as
Aging (PVTA). The key components of the proposed approach are in-situ delay
monitors (Pre-Error flip-flops), detecting late but still non-erroneous signal transi-
tions(pre-errors).Basedonthemeasuredpre-errorrate,thevoltageisadjustedwith
a low-overhead control unit connected to the on-chip voltage regulator. This way
powerconsumptionisoptimized,byexploitingunusedtimingmargin,producedby
state-of-the-artworst-casedesigns.
The presented Pre-Error AVS scheme adapts the voltage during normal circuit
operation (on-line) and hence no test intervals, nor interaction with higher system
levels is required. To describe the statistics of the closed-loop voltage control, a
Markovchainmodelwasdeveloped,whichisbasedontransistorlevelsimulations.
Withthismodel,thepowersavingpotentialaswellastheriskofovercriticalvoltage
reductions can be analyzed very efficiently. Furthermore, the Markov model was
extendedinordertoevaluatetherobustnessofthecontrol-loopagainstglobaland
localvariations.
The elaborated approach was tested on an arithmetic and an image processing
circuit,bothsynthesizedinanindustrial65nmlow-powerCMOStechnology.For
thetwodesignsthePre-ErrorAVSconceptachievesdynamicpowersavingsof25%
(includingalloverheads)whileensuringanerrorratebelow1E-9.Atthesametime
theleakagepowerisreducedbyover30%.
Munich,Germany MartinWirnshofer
v
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 SourcesofVariation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 ProcessVariations . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 ImperfectionsoftheManufacturingProcess . . . . . . . . 6
2.1.2 GlobalandLocalProcessVariations . . . . . . . . . . . . 7
2.1.3 ImpactofProcessVariationsonDigitalCircuits . . . . . . 7
2.2 VoltageVariations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 OriginofVoltageFluctuations. . . . . . . . . . . . . . . . 10
2.2.2 ImpactofVoltageChangesonthePathDelay . . . . . . . 11
2.3 TemperatureVariations . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1 HotCarrierInjection(HCI) . . . . . . . . . . . . . . . . . 12
2.4.2 BiasTemperatureInstability(BTI) . . . . . . . . . . . . . 12
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 RelatedWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 DynamicVoltageScaling . . . . . . . . . . . . . . . . . . . . . . 15
3.2 AdaptiveVoltageScaling . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 AVSbyReplicaPaths . . . . . . . . . . . . . . . . . . . . 16
3.2.2 RazorConcept . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.3 Pre-ErrorAVS . . . . . . . . . . . . . . . . . . . . . . . . 19
4 AdaptiveVoltageScalingbyIn-situDelayMonitoring . . . . . . . . 23
4.1 PrincipleofOperation . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 OverallAVSControlLoop . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 DigitalCMOSCircuit . . . . . . . . . . . . . . . . . . . . 24
4.2.2 In-situDelayMonitor . . . . . . . . . . . . . . . . . . . . 26
4.2.3 AVSControlUnit . . . . . . . . . . . . . . . . . . . . . . 27
4.2.4 VoltageRegulator . . . . . . . . . . . . . . . . . . . . . . 28
vii
viii Contents
5 DesignofIn-situDelayMonitors . . . . . . . . . . . . . . . . . . . . 31
5.1 Delay-ElementBasedPre-ErrorFlip-Flop . . . . . . . . . . . . . 31
5.2 Duty-CycleBasedPre-ErrorFlip-Flops . . . . . . . . . . . . . . . 34
5.2.1 DynamicImplementation . . . . . . . . . . . . . . . . . . 35
5.2.2 StaticImplementation . . . . . . . . . . . . . . . . . . . . 39
5.3 ComparisonofIn-situDelayMonitors . . . . . . . . . . . . . . . 41
6 ModelingtheAVSControlLoop . . . . . . . . . . . . . . . . . . . . 45
6.1 SimulationMethodology . . . . . . . . . . . . . . . . . . . . . . 45
6.2 MarkovModelofthePre-ErrorAVSSystem . . . . . . . . . . . . 48
6.2.1 StatisticsoftheVoltageControl . . . . . . . . . . . . . . . 48
6.2.2 PowerSaving . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2.3 TimingErrorRate . . . . . . . . . . . . . . . . . . . . . . 55
6.3 StabilityoftheControlLoop . . . . . . . . . . . . . . . . . . . . 57
7 EvaluationofthePre-ErrorAVSApproach . . . . . . . . . . . . . . 61
7.1 PowerSavingPotentialandReliability . . . . . . . . . . . . . . . 61
7.1.1 VoltageAdaptationUnderGlobalVariations . . . . . . . . 61
7.1.2 TotalPowerSavingswithPre-ErrorAVS . . . . . . . . . . 64
7.1.3 VoltageAdaptationUnderLocalVariations . . . . . . . . . 65
7.1.4 RoleofIn-situDelayMonitors . . . . . . . . . . . . . . . 65
7.2 ApplicationofPre-ErrorAVSforanImageProcessingCircuit . . . 67
7.2.1 DiscreteCosineTransform(DCT)Circuit . . . . . . . . . 68
7.2.2 PowerandPerformanceAnalysis . . . . . . . . . . . . . . 69
8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.1 MathematicalDerivation:PathDelayUnderLocalVariations . . . 77
A.2 Two-DimensionalDCTTransform . . . . . . . . . . . . . . . . . 77
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Abbreviations and Symbols
Abbreviations
AVS AdaptiveVoltageScaling
BTI BiasTemperatureInstability
CD CriticalDimension
CLK Clocksignalfordigitallogic
DC-DC DirectCurrenttoDirectCurrent
DCT DiscreteCosineTransform
DFT DiscreteFourierTransform
DIBL Drain-InducedBarrierLowering
DVFS DynamicVoltageFrequencyScaling
DVS DynamicVoltageScaling
EDA ElectronicDesignAutomation
FF Flip-Flop
FO Fan-Out
HCI HotCarrierInjection
HDL HardwareDescriptionLanguage
IC IntegratedCircuit
IDCT InverseDiscreteCosineTransform
ITRS InternationalTechnologyRoadmapforSemiconductors
LDO Low-Dropout
LER LineEdgeRoughness
LLN LawofLargeNumbers
MC Monte-Carlo
MOSFET Metal-Oxid-SemiconductorField-Effect-Transistor
NBTI NegativeBiasTemperatureInstability
OPC OpticalProximityCorrection
PBTI PositiveBiasTemperatureInstability
PCM ProcessControlMonitoring
PSM Phase-ShiftMasks
PVT Process,VoltageandTemperature
PVTA Process,Voltage,TemperatureandAging
ix
x AbbreviationsandSymbols
PWCL Pulse-WidthControlLoop
RDF RandomDopantFluctuations
RTL Register-TransferLevel
SoC System-on-Chip
SPICE SimulationProgramwithIntegratedCircuitEmphasis
STA StaticTimingAnalysis
TGMS Transmission-GateMaster-Slave
TOX ThicknessofthegateOxid
VHDL Very-high-speedintegratedcircuitHardwareDescriptionLanguage
Symbols
a FittingparameterfortheCMOSdelaymodel
α Switchingactivityindigitalcircuits
A Matchingparameterfortransistorcurrent
Δk/k
A Matchingparameterforthresholdvoltage
ΔVt
b FittingparameterfortheCMOSdelaymodel
b DigitsoftheVoltageLevelcontrolword
i
C Perunitareaoxidecapacitance
ox
C Loadcapacitanceoftheswitchinggates
switch
ΔV VoltagestepsizeoftheAVSregulator
DD
ΔV Voltagebounceduetodi/dtnoise
di/dt
ΔV VoltagebounceduetoIR-drop
IRdrop
ΔP Uncertaintyofthetimingerrorrate
err
f Clockfrequency
i Time-varyingcurrent
I DrainCurrent
D
I Leakage/staticcurrent
leak
I Off-statecurrentofMOSFETs
off
I On-statecurrentofMOSFETs
on
k CurrentfactorofMOSFETs
L Transistorlength
L Parasiticinductance
parasitic
μ Carriermobility
N Numberofclockcyclesperobservationinterval
nlimit↓ Lowerthresholdforthepre-errorcount
nlimit↑ Upperthresholdforthepre-errorcount
n Pre-errorcountduringanobservationinterval
pre
n Meanpre-errorcountduringanobservationinterval
pre
P Markovmatrix
P Timingerrorrate
err
P Nominaltimingerrorrate
err,nom
P Dynamicpowerconsumptionofdigitalcircuits
dyn
π Stationary(steady-state)probabilityvector
P Leakage/Staticpowerconsumptionofdigitalcircuits
leak
P Pre-errorprobability
pre
P Totalpowerconsumptionofdigitalcircuits
total
AbbreviationsandSymbols xi
P ProbabilityforacertainvoltagelevelV
VDD DD
PVDD↓ ProbabilitythatthesupplyvoltageVDD isdecreased
PVDD→ ProbabilitythatthesupplyvoltageVDD ismaintained
PVDD↑ ProbabilitythatthesupplyvoltageVDD isincreased
R Resistanceofthepowergrid
grid
σ Standarddeviation
τ Timeconstantofthevoltageregulator
t Pathdelay
d
t Maximumpathdelay
d,max
t Gatedelay
gate
T Temperature
T Clockperiod
Clk
T Lengthofthepre-errordetectionwindow
pre
T Setuptime
setup
T Timingslack
slack
V Supplyvoltage
DD
V Nominalsupplyvoltage
DD,nom
V DrainSourceVoltage
DS
V GateSourceVoltage
GS
V Referencevoltage
ref
V Thresholdvoltage
t
W Transistorwidth