Unleash the System On Chip using FPGAs and Handel C

183 Pages·2009·3.37 MB·English

by  Rajanish K. Kamat

Unleash the System On Chip using
FPGAs and Handel C
Unleash the System
On Chip using FPGAs
and Handel C
Rajanish K. Kamat • Santhosh A. Shinde •
Vinod G. Shelake
Authors
Department of Electronics
Shivaji University, Kolhapur
India
1 3
Authors
Dr. Rajanish K. Kamat Mr. Vinod G. Shelake
Department Electronics Department Electronics
Shivaji University Shivaji University
Kolhapur-416004 Kolhapur-416004
India India
E-mail: [email protected]
Mr. Santhosh A. Shinde
Department Electronics
Shivaji University
Kolhapur-416004
India
ISBN: 978-1-4020-9361-6 e-ISBN: 978-1-4020-9362-3
Library of Congress Control Number: 2008942203
© Springer Science+Business Media B.V. 2009
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Preface
With the rapid advances in technology, the conventional academic and research
departments of Electronics engineering, Electrical Engineering, Computer Science,
Instrumentation Engineering over the globe are forced to come together and update
their curriculum with few common interdisciplinary courses in order to come out
with the engineers and researchers with muli-dimensional capabilities. The grow-
ing perception of the ‘Hardware becoming Soft’ and ‘Software becoming Hard’
with the emergence of the FPGAs has made its impact on both the hardware and
software professionals to change their mindset of working in narrow domains. An
interdisciplinary field where ‘Hardware meets the Software’ for undertaking seem-
ingly unfeasible tasks is System on Chip (SoC) which has become the basic plat-
form of modern electronic appliances. If it wasn’t for SoCs, we wouldn’t be driving
our car with foresight of the traffic congestion before hand using GPS. Without the
omnipresence of the SoCs in our every walks of life, the society is wouldn’t have
evidenced the rich benefits of the convergence of the technologies such as audio,
video, mobile, IPTV just to name a few. The growing expectations of the consumers
have placed the field of SoC design at the heart of at variance trends. On one hand
there are challenges owing to design complexities with the emergence of the new
processors, RTOS, software protocol stacks, buses, while the brutal forces of deep
submicron effects such as crosstalk, electromigration, timing closures are challeng-
ing the design metrics. Moreover the time to market pressure, process roadmap
acceleration, mixed design flows have posed various challenges to the SoC designer
community. The present book ‘Unleash the System On Chip using FPGAs and
Handel C’, attempts to address few challenging issues of SoC design leveraging the
FPGA platform with ‘C’ based programming methodology.
Organization of the book
The book is divided into seven chapters. Chapter 1 introduces the concept of SoC.
It visualizes the unique place of the SoC in the microelectronics arena and covers
the market trends, challenges and opportunities for the budding professionals in this
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vi Preface
field. Chapter 2 covers the essential details of the Handel C, which is extensively
used in the book for making software hard. The third chapter presents details of
sequential circuit design with appropriate case studies. The fourth chapter details
the combinational system designing from the SoC viewpoint on the Xilinx FPGA
platform. Chapter five throws light on placing the algorithms in the SoC paradigm
using Xilinx EDK platform with emphasis on ‘Hardware-Software Codesign’.
Chapter six is on the theme of rapid prototyping with unique design realizations
of fuzzy logic controller, Network on Chip and ciphers. Chapter seven extends the
same theme, however with a different approach of using soft processor cores.
The book is carved for all those who wish to be SoC designers with relatively less
steep learning curve. One of the striking features is one can possibly realize the designs
presented here with simple setup and free open source tools such as system C.
In these economically turbulent times, escalating efficiency and dropping risk while
continuing to innovate would be decisive for the SoC professionals and industries
to ride out the economic slowdown. We are sure that this book will definitely serve
as ‘Light House’ to guide the SoC designer community.
Interacting through blog and website
A blog is created by the authors exclusively to interact with the readers of this book.
The URL for the blog is: http://drkamat.wordpress.com/ . We are looking forward
towards your posts, comments and design queries on this blog. The readers may as
well see the updates and the upcoming SoC cores at the Author’s homepage at URL:
http://www.rkkamat.in
Foreword
System-on-chip technology (SoC) is a truly innovative and creative realm of VLSI
that brings multiple functions integrated on a single silicon chip. According to the
electronics.ca research network, the SoC Technology market is currently estimated
at nearly $14.4 billion. The prophecy is further growth, with an average annual
growth rate of 24.6%, reaching around $43.2 billion by 2009 i.e. by next year. The
market statistics mentioned above gives an insight as regards to this important and
ever growing segment of VLSI technology. The SoC with phenomenal growth rate
is experiencing many challenges from the designer point of view such as narrowing
development cycle without compromising the product functionality, performance,
reliability and quality. The computational complexity makes the SoCs to stand apart
in the crowd of the custom and semicustom systems and poses unique challenges to
the designers that can be described as “More than Moore” or “greater than equal to
Moore”. While the major players in this field like Infineon, Motorola, Intel, Wipro
are achieving an annual growth rate of more than 100%, still the industry is evidenc-
ing “More is Less” with ubiquitous penetration of SoCs in every walk of society.
How does the academic, research and industry keep up with the growing chal-
lenges of SoCs? Here is a book that rightly focuses on the issues pertaining to
digital SoCs. It is a sort of brainstorming at the top level and then percolating the
same at the individual modules with top-down approach. This is the challenge that
Dr. Kamat and his research team faced when they were exploring various aspects of
this field. Therefore, they have come out with a book that presents their hands-on
experiences with digital SoCs. The book in its unique fashion addresses the design
issues, technological challenges, and market legacies by presenting a distinctive
know-how based on FPGAs and C based methodology.
The approach presented in the book is multifaceted. It is solidly grounded on
a tripod approach comprising of Xilinx FPGAs, Handel C and soft IP cores. Dr.
Kamat weds the trio with practical case studies and came out with a good number
of building blocks to build successful design. It is vital to appreciate that the digital
semi-custom design is not a straightforward process, especially in the backdrop of
increasing software on the chip which is referred to as ‘Software Parkinson’. The
authors have successfully showcased the hardware software portioning and con-
veyed their notion to the readers.
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viii Foreword
Chapter 1 of the book presents various essential attributes of the SoCs. Exten-
sive survey is conducted by the authors to present the state of the art systems, the
design stats quo and various design and market challenges. Chapter 2 covers various
aspects related to the C based methodology. The screenshots presented here makes
the learning curve less steep for the novice designers. Chapter 3 and 4 presents vari-
ous implementations of the sequential and combinational logic designs respectively.
Chapter 5 gives an insight of customized arithmetic core designs. The striking
feature of this chapter is coverage of Xilinx EDK suite, the no-fee intellectual prop-
erty (IP) cores for designing embedded processing systems with Xilinx platform
FPGAs. Chapter 6 has addressed the fuzzy logic controller and Network on Chip
designs with which the authors have tried to inculcate intelligence on chip. This
is further extended in Chapter 7 with hardware-software codesign methodologies
using soft processor cores to realize the SoC design in narrowing time window.
Thus the authors have endeavored to present more than sufficient details to
encourage the potential readers to dig at depth when dealing with the design prin-
ciples that appears to be institutively obvious. Undoubtedly the design community
could use the book to discover the programming concepts that actually aids in real-
izing the SoCs. They can as well extend the design methodologies presented in this
book with the Open System C initiatives (OSCI) with the recent transaction-level
modeling standard, TLM-2.0 that enables model interoperability and reuse, pro-
viding an essential framework for architecture analysis, software development and
performance analysis, and hardware verification. Thus in lieu of the Handel C, the
designers can apply TLM-2.0 (which is freely downloadable) to show their SoCs
the light of the day.
To sum up I would like to quote that “ The only constant in life is change” which
is experienced in its real sense in the field of SoCs through Moore’s law in Moore’s
own words, “Several times along the way, I thought we reached the end of the line,
things tapered off, and our creative engineers come up with ways around them.”
The designer community will definitely appreciate that the present book is a piece
of creative engineering.
I wish all the best to the potential readers to realize their SoCs with the know-how
presented in the book.
Yogindra S Abhyankar
Yogindra S. Abhyankar is a Group coordinator working with the
hardware technology development group, Center for Development
of Advanced Computing (C-DAC), Pune, India for more than 14
years. He has worked on various projects in high performance
computing (HPC) involving high speed inter-connects, system
architecture and VLSI design. His current field of research is in
the area of “Reconfigurable Computing”, one of the emerging
approaches for speeding-up HPC applications. He holds a MS degree from the
University of Wisconsin, USA.
Author’s Profile
Dr. Rajanish K. Kamat is working as a Reader in the Department
of Electronics, Shivaji University, Kolhapur, India. He enjoys
teaching to Masters in Electronics and Masters in Technology
classes. He is supervising number of research students working
towards their doctorate in the area of VLSI Design. The unique-
ness of his research work is its application orientation achieved
through the analytical marriage of interdisciplinary themes such
as neural network, Computational Techniques, Software etc. He has published his
research work widely in the areas of Sensor Systems, VLSI Design, Embedded Sys-
tems, Network Security and Visualization techniques. He is recipient of Research
Grants under the ‘Young Scientist Scheme’ from the Department of Science and
Technology of Government of India. He is referee of good number of reputed
research journals.
Mr. Santosh A. Shinde is working as a Research Fellow under
the University Grants Commission scheme at Department of
Electronics, Shivaji University, Kolhapur. He is also pursuing his
Doctorate in the research area of VLSI Design which is in the
final phase. His thesis topic is “Programmable ASIC Design for
Circumventing SPAM”. He also carries with him rich industrial
experience in various branches of VLSI Design and Embedded
Systems. He has published good number of research papers in referred International
Journal of repute.
Mr. Vinod G. Shelake is working as a Lecturer at Sanjivani
College, Panahala. He is also pursuing his Doctorate in the area of
VLSI Design. His thesis topic is “FPGA based Firewall Design”.
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Acknowledgements
Many people motivated us to make this book possible. At the outset authors would
like to acknowledge the grants received under DST-SERC Fast Track Project for
Young Scientist SR/FTP/ETA-14/2006 entitled “Development of FPGA based open
source soft IP cores for parameterized microcontroller design” to Dr. R.K. Kamat
under which a grand repository of free SoC cores on web is coming up. Interested
readers may keep a track on the web URL: http://www.rkkamat.in
Dr. Kamat owes great thanks to his teacher Dr. G.M. Naik for his inspiring sup-
port. Thanks are also due to Mr. Jivan Parab who will be coauthor in forthcoming
interesting books on VLSI design. Thanks also go to authorities of Shivaji Univer-
sity, Kolhapur for the support received towards the infrastructure. Special thanks to
Mr. Yogindra Abhyankar, CDAC Pune for reviewing the book and agreeing to give
the foreword.
Dr, Kamat would also like to thank his wife Rucha, parents, students, friends and
supporters for their support. Again special thanks to Adeet and Pari Shanbhag for
their enjoyable company that relieved the stress of SoC designing.
Finally, special thanks to Mr. Mark de Jongh, Senior Publishing Editor and Mrs.
Cindy Zitter from Springer for their outstanding support all the time. It is only
because of them we feel like contributing quality work to the designer community
through the reputed network of ‘Springer’.
- Dr. R.K. Kamat
- Mr. Santosh A. Shinde
- Mr. Vinod G Shelake
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Prologue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Exceptional Attributes of the SoC Technology. . . . . . . . . . . . . . . . . . . 2
1.3 Classical Taxonomy: A Holistic Perspective Extended Towards
Integrated Circuits Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 System-on-Chip (SoC) Term and Scope. . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Constituents of SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.1 Processor Cores for SoC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.2 On Chip Memory in SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.3 SoC Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.4 Timing References for SoC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.5 Voltage Regulator and Power Management Circuits . . . . . . . . 14
1.5.6 On Chip ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6 Sprawling Growth of SoC Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7 Choosing the Platform, ASIC vs. FPGAs. . . . . . . . . . . . . . . . . . . . . . . 16
1.7.1 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.7.2 Standard Cell Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.7.3 Design Based IP-Cores, Hard and Soft Macros . . . . . . . . . . . . 18
1.7.4 SoC Through SemiCustom ASICs . . . . . . . . . . . . . . . . . . . . . . 18
1.7.5 SoC Realization Through Structured ASIC . . . . . . . . . . . . . . . 19
1.8 FPGA Based Programmable SoC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.9 Orientation of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.9.1 Approach Adopted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.9.2 Motivation Behind the Approach . . . . . . . . . . . . . . . . . . . . . . . 21
1.9.3 Setup Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Familiarizing with Handel C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 EDA Tools i.e. Computer Aids for VLSI Design . . . . . . . . . . . . . . . . . 25
2.2 Background of Hardware Description Languages . . . . . . . . . . . . . . . . 26
2.3 Expressing Abstraction at Higher Levels . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Where C Stands Amidst the Well Established HDLs? . . . . . . . . . . . . . 28
2.5 Introducing Handel C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6 Top Down or Bottom up? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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