Universal Computer Interfaces

375 Pages·1988·17.637 MB·English

by  R.F.B.M. Dheere

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Universal
Computer Interfaces
R. F. B. M. DHEERE
European Patent Office
The Hague, The Netherlands
PERGAMON PRESS
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Copyright © 1988 The European Patent Office
All Rights Reserved. No part of this publication may be
reproduced, stored in a retrieval system or transmitted in any form
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First edition 1988
Library of Congress Cataloging in Publication Data
Dheere, R.F.B.M.
Universal computer interfaces/R.F.B.M. Dheere. — 1st ed.
p. cm. — (EPO applied technology series; v. 11)
Bibliography: p.
Includes index.
1. Computer interfaces. I. Title. II. Series.
TK7887.5.D44 1988
004.6—dcl9 88-15288
British Library Cataloguing in Publication Data
Dheere, R.F.B.M.
Universal computer interfaces.—(EPO
applied technology series; v. 11).
1. Computers. Interfaces
I. Title II. Series
004.6
ISBN 0-08-036610-4
Printed in Great Britain by A. Wheaton & Co. Ltd., Exeter
Preface
This monograph alms to present a survey of developments in the field of
the universal computer Interface. This interface should be the same for
all peripheral devices and is device-independent. Peripheral device
dependent logic is not directly treated in this monograph.
This book is the result of a study of the patent search-files of the
European Patent Office (EPO) at The Hague in the IPC (International Patent
Classification) class G06F.
Since there are thousands of relevant documents, this survey cannot refer
to all of them and a selection had to be made, to choose those documents
which I thought best Illustrated the state of the art. The documents are
listed according to certain parameters, subjects, etc. This implies that a
single document may be referred to more than once. The documents have been
abstracted. If one 1s of particular interest, greater detail and further
embodiments can usually be obtained from the full version,of which a copy
can be ordered.
This monograph Is divided into five chapters. Chapter I deals with the
basic interface structure. Chapter II defines the parameters and common
characteristics of the interface. Some of the most important industrial
bus realizations are described in Chapter III. Chapter IV retraces some
special improvements and the last chapter describes the universal
interface adapter circuit.
General references; lists of cited patent documents, patentees and
inventors as well as a subject index can be found at the end of the book.
I have been extremely fortunate in having the help of many people during
the course of this project. I would especially like to thank Mr Chugg for
reading the manuscript and making helpful suggestions. I also wish to
express my gratitude to Mr Oey, Director at the EPO; Messrs Feuer, Guivol,
Lepee and Wanzeele, all examiners at the EPO, for the contribution of
their ideas.
A special acknowledgement is given to Mr Pico for the photographic work
and to Mrs Bruggeman who did the immense amount of secretarial work.
Finally, I would like to thank my wife Mimi for her endless patience while
I spent untold hours in writing this monograph.
R. Dheere
Note on Cited
Patent Documents
In this monograph, a great number of patents and published patent
applications *) are cited, using an international two-letter country code,
i.e. :
DE = Germany (Federal Republic)
EP - European Patents (or patent applications)
FR * France
GB - United Kingdom
JP « Japan **)
US « United States of America
WO » International Bureau of NIPO (Patent applications published
under the Patent Cooperation Treaty (PCT)
The patent literature covered by the search files of the European
Patent Office at The Hague encompasses patent publications of
following countries or offices : Australia, Austria, Canada, France,
Germany (Federal Republic), Japan, Switzerland, United Kingdom, USA,
USSR, European Patent Office, World Intellectual Property Organizat­
ion, African Intellectual Property Organization, Belgium, Luxemburg,
and The Netherlands.
All cited patent documents are published patent applications (KOKAI
TOKKYO).
vi
CHAPTER I
Basic Interface Structure
A typical example of a basic interface structure between two terminals is
described in US 3336582 [IBM].
-·/'
BUS OUT ( 9 LUES >
BUS OUT POSITIONS ?, 0. 1.
2.3.4.5.S I 1
M.YI
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8JS IN PCSinONS P. 0. 1
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TERMINAL ADOHESS IN —c? TERMINAL
STATJS iN~ *4
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*= V SEliCTiON CONTROLS \1 III
/ SELECT 0U T _ ? 0 =·
V OHOPELDR ATIOOUNTA L 56O UT «J8'a-
SUPPRESS OUT 60"
SEtECT IN-3?
REQUEST iN~70
OPERATIONAL IN — 7?
The transfer of data between the two terminals requires a number of extra
signals : address signals (26a, 28a) for the selection of a terminal
(interface adapter circuit) and of an I/O device connected with that
terminal, tag signals (26b, 28b) and selection control signals (26c, 28c).
A separate bus (bus out, bus in) is provided in each direction (26a, 28a)
for the address, data and control information (9 lines with 1 parity line).
1
2 UNIVERSAL COMPUTER INTERFACES
Inbound and outbound tag signals define the kind of information (data,
address, control information) transferred on bus out, bus in (6 lines).
Extra selection control signal (7 lines) also use unidirectional lines.
The rise and fall of all signals transmitted over this interface are
controlled by corresponding interlocked responses. A total of 31 lines are
used to control data movement. This example (as employed in the IBM/360
computers) is only given as an illustration of the complexity of a basic
interface structure, without describing the functional behaviour.
The following parameters define interface behaviour :
the network configuration of data lines, address lines, control lines,
e.g. star configurations, bus configurations, matrix network
configurations;
the synchronization of the processor activities to the external
events, e.g. programmed I/O, Channel/DMA;
the interface access arbitration;
the interface width, e.g. parallel lines or a serial line;
the interface transfer timing, e.g. synchronous or asynchronous
transfer;
the error treatment;
the physical realisation.
These parameters will be considered more extensively in Chapter II.
An optimal combination of these parameters may limit the enormous number
of theoretically possible Interface designs to a reasonable number of
practical designs by applying the following criteria :
efficiency (data speed, number of peripheral devices, reaction time,
maximum line length);
cost (number of connectors, number of lines);
integrity, reliability (error suppression, failsafe behaviour);
extensibility permitting ease of modification and ease of growth
(configuration) and ability to tolerate devices to be connected and
disconnected while the overall system is running i.e. live insertion
and withdrawal;
ability to interconnect devices of different architectures and from
different manufacturers (OSI - Open System Interconnect).
Two different basic computer system structures can be distinguished in
which basic interface structures can be applied. *)
Device interfaces or device dependent logic arrangements which are
dedicated to a specific type of device are not directly treated in
this monograph. These device-interfaces directly control a specific
device (e.g. printer, keyboard) by special bit commands (e.g. printer
start-stop commands).
BASIC INTERFACE STRUCTURE 3
A system with separate interfaces for memory (e.g. memory bus) and for
peripheral devices (e.g. peripheral or I/O bus) and a system with a common
interface for memory and peripheral devices.
An example of the first type of system is described in
US 3376554 and US 3999163 [DEC]
w
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w
PUNCH
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42
onve
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4CT\A FAST
HPUrAwurj ^JB^jTv EX 34
'"SKST" SBSS
Three memory buses (30, 47, 53), two I/O buses (36, 51) and a device bus
(46) (also to be considered as as I/O bus) can be distinguished.
An example of the second type of system is given in US 3470542 [WANG].
The common bus lines (10) form the common interface.
COMMON BUS LINES
INTERFACE NTERFACE INTERFACE INTERFACE INTERFACE INTERFACE
UNIT UNIT UNIT _ UNIT _. UNIT .. UNIT _.
, 1 < | • •
TAPE HARD CORE
UNIT KEYBOARO PRINTER CALCULATOR WIRE COUNTER MEMORY
- /J 14 PROGRAM /5 Ί
4 UNIVERSAL COMPUTER INTERFACES
A multiprocessor (multicomputer) system structure can also be implemented
as a system with separate interfaces.
WO 81/02643 [JEUMONT-SCHNEIDER]
Computers (1, 7, 8, 9) with local
memories (2, 10, 11, 12) are connected
to a main memory (6) by a memory bus
(5) (first interface) and are
;
^i additionally interconnected by an
M electronic switch (second interface),
to substantially increase the message
transmission speed between them.
IP
> u
!■ " *
!' e.
JE
Peripheral devices are coupled to an interface structure by an interface
adapter circuit.
Two kinds of interface adapter circuits can be distinguished : specific or
universal. The universal interface adapter circuit will be extensively
treated in Chapter V.
An interface adapter circuit can be a --7
specifically designed hard wired CPU
adapter unit for each different type 1
. ..-μ
of peripheral device. This type of
adapter circuit is described in US
3432813 [IBM] as a variety of control
units CU (15), each control being
connected to a number of input/output
devices (16) of the same specific
type.
BASIC INTERFACE STRUCTURE 5
A universal interface adapter circuit as represented in US 3828325
[HONEYWELL INFORMATION SYSTEMS] has been developed which has universal
interfacing capabilities by adapting to the peripheral device rather than
requiring that the device adapt to a common interface.
3AS/C
DATA /i au/r
OA//r sroee (ecu)
peocepueAL
ΑΟΑΡΓΑΤ/ΟΛ/ τ
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ΙΛ/Pur /ourpor ΡΟΛΤ £/Λ//Γ
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srAae
Χ£Τ3ΰΑ/Ζθ/ό£Γ tereoA/eo/aGr
re&M/A/AL re/eM/ASAc
The basic logic unit (BLU) programs the input/output ports (11) as
having input and/or output leads, designates the selected leads as data or
control leads, and operates the leads for the information to be
transmitted either serially or in parallel. The signal parameters of these
leads are firmware programmable to control the pulse widths, the signal
frequencies, the signal identity, and the number of leads allocated to
each peripheral device.
Another universal interface adapter circuit is described in US 3714635
[IBM].
Fig. 1
CPU
CONTROL
UNIT
^__I
STANDARD STANDARD iSTANDARD
ADAPTER ADAPTER ! ADAPTER
4—Γ I/O I/O Γ " Ί I/Q~M