Timing Optimization Through Clock Skew Scheduling

273 Pages·2009·6.776 MB·English

by  Ivan S. Kourtev, Baris Taskin, Eby G. Friedman (eds.)

Timing Optimization Through Clock
Skew Scheduling
Ivan S. Kourtev • Baris Taskin • Eby G. Friedman
Timing Optimization
Through Clock Skew
Scheduling
ABC
IvanS.Kourtev BarisTaskin
UniversityofPittsburgh DrexelUniversity
Pittsburgh,PA Philadelphia,PA
USA USA
EbyG.Friedman
UniversityofRochester
Rochester,NY
USA
ISBN:978-0-387-71055-6 e-ISBN:978-0-387-71056-3
DOI:10.1007/978-0-387-71056-3
LibraryofCongressControlNumber:2008937987
(cid:176)c SpringerScience+BusinessMedia,LLC2009
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Preface
History of the Book
The last three decades have witnessed an explosive development in in-
tegrated circuit fabrication technologies. The complexities of current CMOS
circuitsarereachingbeyondthe65nanometerfeaturesizeandmulti-hundred
million transistors per integrated circuit. To fully exploit this technological
potential, circuit designers use sophisticated Computer-Aided Design (CAD)
tools.Whilesupportingthetalentsofinnumerablemicroelectronicsengineers,
these CAD tools have become the enabling factor responsible for the success-
ful design and implementation of thousands of high performance, large scale
integrated circuits.
Thisbook(aresearchmonograph)originatedfromabodyofdoctoraldis-
sertationresearchcompletedbythefirstauthorattheUniversityofRochester
from1994to1999whileunderthesupervisionofProf.EbyG.Friedman.This
research focuses on issues in the design of the clock distribution network in
largescale,highperformancedigitalsynchronouscircuitsandparticularly,on
algorithmsfornon-zero clockskewscheduling.Duringthedevelopmentofthis
research, it became clear that incorporating timing issues into the successful
integratedcircuitdesignprocessisoffundamentalimportance,particularlyin
that advanced theoretical developments in this area have been slow to reach
the designers’ desktops. The second edition of the book is enhanced by the
body of doctoral dissertation research completed by the second author at the
University of Pittsburgh from 2000 to 2005 under the supervision of Prof.
Ivan S. Kourtev. This dissertation focuses on advanced timing, synchroniza-
tion and design methodologies based on non-zero clock skew scheduling. In-
cluded in this book are methods on the applicability of clock skew scheduling
oncircuitswithlevel-sensitivelatches,atiming-drivencircuitdesignmethod-
ology to attain the maximum performance out of clock skew scheduling and
a solution to non-zero clock skew scheduling problem in a parallel comput-
ing environment, specifically derived for integration into the physical design
process of an emerging non-zero clock skew clocking technology.
V
VI Preface
It is the authors’ belief that the successful application of non-zero clock
skew scheduling techniques to the integrated circuit design process can only
followadetailedunderstandingoftheoperationofintegratedcircuitsatmany
different levels—from device physics through system architecture to packag-
ing. While a detailed coverage of all of these topics in a single text is im-
practical,anhonestefforthasbeenmadetoprovideanin-depthtreatmentof
all of those areas closely related to the clock skew scheduling techniques pre-
sented in this book. Tutorial chapters on the structure and design of modern
integrated circuits, as well as on the fundamental principles of signal delay
are included in this text since these topics are crucial to understanding clock
skew scheduling in general. The information presented in these tutorial chap-
terscanalsoquicklyfamiliarizethereaderwiththeproblems,definitions,and
terminology used throughout the book.
Automated methodologies for synchronous circuit performance optimiza-
tion through clock skew scheduling is the primary topic presented in this
book. The objectives of these methodologies are to improve the performance
(specifically,theoperatingfrequencyorspeed)whileincreasingthereliability
of fully synchronous digital integrated circuits. Traditionally, design wisdom
has dictated the use of global zero clock skew. In the research presented here,
however, non-zero clock skew scheduling is exploited. A set of algorithms to
accomplishthisobjectiveareconsideredinmoredetail.Specifically,thisbook
deals in depth with the following issues:
• Amethodologyforsimultaneousnon-zeroclockskewschedulinganddesign
of the topology of the clock distribution network. This methodology is
basedonthepioneeringworksofFriedman[1]andFishburn[2],andbuilds
onLinearProgramming(LP)solutiontechniques.Thenon-zeroclockskew
schedulingofcircuitswithlevel-sensitivelatchesandformulti-phaseclock
signals is formulated as a LP problem. The simultaneous clock scheduling
andclocktreetopologysynthesisproblemisformulatedasamixed-integer
linear programming problem that can be solved efficiently. The proposed
algorithms have been evaluated on a variety of benchmark and industrial
circuits and synchronous performance improvements of well above 60%
have been demonstrated.
• For those cases where reliable circuit operation and production yield are
the highest level priorities, an alternative problem formulation is devel-
oped. This formulation is based on a quadratic (hence the QP—quadratic
programming)measure,orcostfunction,ofthetoleranceofaclocksched-
ule to parameter variations. A mathematical framework is presented for
solving the constrained and bounded QP problem. A constrained ver-
sion of the problem is iteratively solved using the Lagrange multipliers
method. As these research issues are topics of great practical importance
for input/output (I/O) interfacing and Intellectual Property (IP) blocks,
explicit clock delay and skew requirements are fully integrated into the
mathematical model described here.
Preface VII
• The theoretical derivation of the limits on the improvements on the clock
periodavailablethroughclockskewscheduling.Thetheoreticalderivation
is performed by identifying the limits for three local data path topologies.
A methodology to mitigate the limitation of clock skew scheduling for a
reconvergent path system is presented. The methodology involves delay
insertiononsomedatapathsofthereconvergentsystemandisformulated
as an LP problem for an automated application.
• Apractical(andnecessary)implementationofclockskewschedulingforan
emerging clock generation and distribution technology in resonant rotary
clocking technology. Preliminary efforts in modeling and implementation
are demonstrated. Details are included on the integration of clock skew
scheduling into a complete physical design flow for the automated design
of rotary clock synchronized synchronous circuits.
As with any project of this magnitude, mistakes are likely. To the best
knowledge of the authors, proper credit has been given to everyone whose
workhasbeenmentionedhere,buttheauthorstakefullresponsibilityforany
errors or omissions.
Acknowledgments
The authors would like to thank all of those who have helped writing
andcorrectingearlymanuscriptversionsofthismonograph—fellowcolleagues
and students, as well as the anonymous reviewers who provided important
comments on improving the overall quality of this book. The authors would
also like to thank Dr. Bob Grafton from the National Science Foundation for
supporting the early research projects that have culminated in the writing
and production of this book. We would also like to warmly acknowledge the
assistance and support of Alex Greene and Katelyn Stanne from Springer—
AlexandKatie’spatienceandencouragementhavebeencrucialtothesuccess
of this project.
The research work described in this research monograph was made pos-
sible in part by support from the National Science Foundation under Grant
No. MIP-9423886 and Grant No. MIP-9610108, by a grant from the New
York State Science and Technology Foundation to the Center for Advanced
Technology-Electronic Imaging Systems, and by grants from the Xerox Cor-
poration, IBM Corporation, Intel Corporation and Multigig Inc.
Pittsburgh, PA, Ivan S. Kourtev
Philadelphia, PA, Baris Taskin
Rochester, NY, Eby G. Friedman
July, 2008
Contents
1 Introduction............................................... 1
2 VLSI Systems ............................................. 7
2.1 Signal Representation .................................... 7
2.2 Synchronous VLSI Systems ............................... 11
2.3 The VLSI Design Process................................. 14
2.4 Summary............................................... 16
3 Signal Delay in VLSI Systems ............................. 19
3.1 Delay Metrics........................................... 19
3.2 Devices and Interconnections ............................. 23
3.2.1 Analytical Delay Analysis .......................... 25
3.2.2 Controlling the Delay .............................. 31
3.2.3 Waveform Effects.................................. 31
3.2.4 Short-Channel Effects.............................. 33
3.2.5 The Importance of Interconnections ................. 35
3.2.6 Delay Mitigation .................................. 37
4 Timing Properties of Synchronous Systems ................ 41
4.1 Storage Elements........................................ 41
4.2 Latches ................................................ 43
4.3 Parameters of Latches.................................... 44
4.3.1 Width of the Clock Pulse........................... 45
4.3.2 Latch Clock-to-Output Delay ....................... 45
4.3.3 Latch Data-to-Output Delay........................ 45
4.3.4 Latch Setup Time ................................. 45
4.3.5 Latch Hold Time.................................. 46
4.4 Flip-Flops .............................................. 47
4.5 Parameters of Flip-Flops ................................. 48
4.5.1 Width of the Clock Pulse........................... 48
4.5.2 Flip-Flop Clock-to-Output Delay .................... 49
IX
X Contents
4.5.3 Flip-Flop Setup Time.............................. 49
4.5.4 Flip-Flop Hold Time............................... 49
4.6 The Clock Signal ........................................ 50
4.6.1 Clock Skew....................................... 52
4.6.2 Multi-Phase Clock Synchronization .................. 53
4.7 Single-Phase Path with Flip-Flops ......................... 55
4.7.1 Preventing the Late Arrival of the Data Signal ........ 55
4.7.2 Preventing the Early Arrival of the Data Signal ....... 58
4.8 Single-Phase Path with Latches ........................... 61
4.8.1 Preventing the Late Arrival of the Data Signal ........ 61
4.8.2 Preventing the Early Arrival of the Data Signal ....... 63
4.9 Multi-Phase Path with Latches............................ 65
4.9.1 Preventing the Late Arrival of the Data Signal ........ 66
4.9.2 Preventing the Early Arrival of the Data Signal ....... 68
4.10 A Final Note ........................................... 69
5 Clock Skew Scheduling and Clock Tree Synthesis .......... 71
5.1 Background............................................. 72
5.2 Definitions and Graphical Model .......................... 73
5.2.1 Permissible Range of Clock Skew.................... 74
5.2.2 Graphical Model of a Synchronous System............ 76
5.3 Clock Scheduling ........................................ 80
5.4 Timing Constraints and Design Automation ................ 85
5.5 Structure of the Clock Distribution Network ................ 86
5.6 Solution of the Clock Tree Synthesis Problem ............... 87
5.7 Software Implementation ................................. 89
5.7.1 Simultaneous Clock Scheduling and Clock
Tree Synthesis .................................... 89
5.7.2 Clock Skew Scheduling............................. 90
6 Clock Skew Scheduling of Level-Sensitive Circuits ......... 97
6.1 Clock Scheduling for Level-Sensitive Circuits................ 97
6.1.1 Latching Constraints............................... 98
6.1.2 Synchronization Constraints ........................ 98
6.1.3 Propagation Constraints ...........................100
6.1.4 Validity Constraints ...............................101
6.1.5 Initialization Constraints ...........................102
6.2 Iterative Approach to Clock Skew Scheduling ...............103
6.3 Linearization of the Timing Analysis.......................104
6.3.1 Modified Big M (MBM) Method ....................105
6.3.2 Linear Programming (LP) Model....................106
6.4 An Example and Experimental Results.....................108
6.4.1 Level-Sensitive Synchronous Circuit State
of Operation......................................110
6.5 Optimality of the LP Formulation .........................113
Contents XI
6.6 Multi-Phase Level-Sensitive Circuits .......................117
6.6.1 Multi-Phase Synchronization Overview...............117
6.6.2 Multi-Phase Level-Sensitive Circuit Timing...........118
6.7 Summary...............................................120
7 Clock Skew Scheduling for Improved Reliability ...........121
7.1 Problem Formulation ....................................122
7.1.1 Clock Scheduling for Maximum Performance..........123
7.1.2 Maximizing Safety.................................125
7.1.3 Further Improvement ..............................127
7.1.4 Clock Scheduling as a Quadratic Programming
Problem..........................................128
7.2 Derivation of the QP Algorithm ...........................129
7.2.1 The Circuit Graph ................................129
7.2.2 Linear Dependence of Clock Skews ..................130
7.2.3 Optimization Problem and Solution..................137
8 Delay Insertion and Clock Skew Scheduling................145
8.1 Limitations on Minimum Clock Period .....................146
8.1.1 Uncertainty of Data Propagation Times ..............147
8.1.2 Data Path Cycles .................................148
8.1.3 Reconvergent Paths................................150
8.2 Delay Insertion Method ..................................152
8.2.1 Motivational Example with a Reconvergent Path ......153
8.2.2 Reconvergence in an Edge-Triggered Circuit ..........153
8.2.3 Reconvergence in a Level-Sensitive Circuit............159
8.2.4 General Reconvergent Data Path Systems ............160
8.3 Linear Problem Formulation ..............................162
8.4 Practical Concerns in Modeling and Application.............163
8.5 Summary...............................................165
9 Practical Considerations...................................167
9.1 Computational Analysis..................................167
9.1.1 Algorithm LMCS-1 ................................169
9.1.2 Algorithm LMCS-2 ................................170
9.1.3 Algorithm CSD ...................................172
9.1.4 Summary of the Proposed Algorithms................175
9.2 Unconstrained Basis Skews ...............................176
9.3 I/O Registers and Target Delays ..........................178
9.4 Summary...............................................181
10 Clock Skew Scheduling in Rotary Clocking Technology ....183
10.1 Resonant Clocking.......................................183
10.1.1 Rotary Traveling Wave Oscillators...................185
10.1.2 Timing Requirements of Rotary Circuits .............189
XII Contents
10.2 Physical Design Flow ....................................191
10.2.1 Timing-Driven Partitioning.........................193
10.2.2 Partitioning with chaco ............................195
10.2.3 Register Insertion for Partitioning ...................196
10.2.4 Clock Skew Scheduling of Partitions .................197
10.2.5 Timing-Driven Register Placement ..................200
10.3 Parallelization of Clock Skew Scheduling ...................202
10.3.1 Speedup of Computation ...........................203
10.4 Summary...............................................203
11 Experimental Results......................................205
11.1 Clock Skew Scheduling of Level-Sensitive Circuits ...........205
11.1.1 Experimental Results on ISCAS’89 Benchmark
Circuits ..........................................206
11.1.2 Verification and Interpretation of Results.............208
11.1.3 Parameter Data Distributions.......................209
11.1.4 Skew Analysis ....................................211
11.2 Multi-Phase Level-Sensitive Circuits .......................213
11.2.1 Multi-Phase Clocking ..............................216
11.2.2 Multi-Phase Clocking Effects on Time Borrowing......219
11.2.3 Multi-Phase Clocking and Clock Skew Scheduling .....220
11.2.4 Simultaneous Time Borrowing and Clock Skew
Scheduling........................................221
11.3 Quadratic Programming (QP) for Maximizing Safety ........223
11.3.1 Description of Computer Implementation.............223
11.3.2 Graphical Illustrations of Results....................225
11.4 Delay Insertion in Clock Skew Scheduling...................225
11.5 Physical Design of Rotary Clock Synchronized Circuits.......233
11.5.1 Clock Skew Scheduling of Partitions Results ..........234
11.5.2 Overall CAD Tool Results..........................237
12 Conclusions................................................243
References.....................................................247
Index..........................................................259