Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology PDF
Preview Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology
Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology Priyanka Kumar i Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology Priyanka Kumar: Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology, September 2011 Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology TTTThhhheeeessssiiiissss submitted in partial fulfilment of the requirements for the degree of Master of Science in Microelectronics by Priyanka Kumar born in Jhansi, India Electronics Research Laboratory Department of Microelectronics & Computer Engineering Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology Several concepts used in this thesis are protected by patents. Copyright © 2011 Priyanka Kumar All rights reserved. Delft University of Technology Department of Microelectronics & Computer Engineering The undersigned hereby certify that they have read and recommend to the Faculty of Electrical Engineering, Mathematics and Computer Science for acceptance a thesis entitled “Time-of-flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology” by Priyanka Kumar in partial fulfillment of the requirements for the degree of Master of Science. Dated: September 9, 2011 Chairman and Co-Advisor: _______________________ prof. dr. ir. Edoardo Charbon Co-Advisor: _______________________ dr. R. Bogdan Staszewski Committee Members: _______________________ dr. ir. Nick van der Meijs _______________________ Andre Borowski Abstract The interest in high performance three-dimensional (3D) imaging has grown in recent years due to immense demand in engineering, science, medicine and entertainment domains. The driving goals of state-of-the-art 3D imagers are high sensitivity to light and fine depth resolution at long range. Furthermore, high level of integration is desirable to achieve low system cost. To meet these demands, the industry has started to transition from traditional analog techniques to standard CMOS based solutions. In this thesis, a novel time-of-flight 3D CMOS imager is proposed. The focus of the design is low power consumption while maintaining human-eye safety requirements. The imager targets security applications, primarily facial recognition, but is also suitable for automotive vision and robotics. In this work, a prototype of a 32x32 pixel array is designed, where each pixel consists of a single-photon avalanche diode as photodetector and a time-to-digital converter (TDC) for fast image acquisition. The imager is expected to achieve millimeter- level depth resolution for range as long as 30 m and has a maximum frame-rate of 1000 fps. Each pixel is constructed within 25x25 µm2 area and has a fill factor of 5.76%. The layout implementation has been carried out in a 65 nm CMOS technology and would be the first of its kind at this process node. vii To my loving parents,
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