Time and Statistical Information Utilization in SAR ADCs

185 Pages·2013·8.12 MB·English

by  Jon Guerber

AN ABSTRACT OF THE THESIS OF
Jon Guerber for the degree of Doctor of Philosophy in Electrical and Computer Engineering
presented on December 4, 2012.
Title: Time and Statistical Information Utilization in High Efficiency Sub-Micron CMOS Successive
Approximation Analog to Digital Converters.
Abstract
Abstract approved:______________________________________________________
Un-Ku Moon

In an industrial and consumer electronic marketplace that is increasingly demanding greater
real-world interactivity in portable and distributed devices, analog to digital converter efficiency
and performance is being carefully examined. The successive approximation (SAR) analog to
digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and
resolution requirements. This is due to the one core single bit quantizer, lack of residue
amplification, and large digital domain processing allowing for easy process scaling. This work
examines the traditional binary capacitive SAR ADC time and statistical information and
proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the
quantizer delay information to enhance accuracy, speed and power consumption of the overall
SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR
(EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer
structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline
configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-
level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR
into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-
stage encoding that not only maintains residue shaping across the binary SAR, but allows for
nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary
SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both
in simulation and with prototype results.
Key Words: SAR ADC, TSAR, Ternary SAR, Residue Shaping, EMCS, FITSAR, R2R DAC
©Copyright by Jon Guerber
December 4, 2012
All Rights Reserved
Time and Statistical Information Utilization in High Efficiency Sub-Micron
CMOS Successive Approximation Analog to Digital Converters

by
Jon Guerber

A THESIS

Submitted to

Oregon State University

in partial fulfillment of
the requirements for the
degree of

Doctor of Philosophy

Presented December 4, 2012
Commencement June 2013
Doctor of Philosophy thesis of Jon Guerber presented on December 4, 2012

APPROVED:

_______________________________________________________________________
Major Professor, representing Electrical and Computer Engineering

________________________________________________________________________
Director of the School of Electrical Engineering and Computer Science

________________________________________________________________________
Dean of the Graduate School

I understand that my thesis will become part of the permanent collection of Oregon State
University libraries. My signature below authorizes release of my thesis to any reader upon
request.

________________________________________________________________________
Jon Guerber, Author
ACKNOWLEDGEMENTS
The journey of my education has not been propelled by my own power. Rather, it’s been
guided, shifted, and directed by many who have worked to influence my environment and
understanding of the world. As Issac newton famously said “If I have seen further, it is only by
standing on the shoulders of giants.” I’d like to take a few pages and thank some of the giants
that have lifted me along my journey (in no particular order). Some of them had long-term
interactions with me and some were brief insights that stuck with me, but they all channeled me
into the path I’m on today.
I’d like to start by thanking my professor Dr. Moon for his guidance, honesty, and genuine
interest in my development. When I first started grad school, I wondered if I was working in the
right group due to the standards and expectations set by Dr. Moon. Yet over time I have come
to realize that his demands are for the benefit and growth of his students and have seen him
make many choices that I’m sure were not in his best interest in terms of funding or recognition,
but fostered growth in me as an engineer and person. If I could do it again, I know I would not
hesitantly join Dr. Moon’s group, but wholeheartedly.
Adding to the benefits of Dr. Moon were his and adjoining research group members
(Manideep Gande, Hari Venkatram, Taehwan Oh, Ben Hershburg, Yue (Simon) Hu, Allen Waters,
Ho-Young Lee, Nima Maghari, Tawfik Musah, Omid Rajaee, Skyler Weaver, Peter Kurahashi,
Sunwoo Kwon, Dave Gubbins, Rob Gregorie, Amr Elshazly, Hurst Kuo, Jacob Postman, Robert
Polawski, Joe Crop, Brian Young and many others). From all of these peers I have gleaned a lot
of what I now know and have talked with them though many of the late nights of graduate
work. Bangda Yang and Brian Drost especially are two that I have talked with in numerous
discussions and to whom I owe much of my understanding of circuits both in my graduate and
undergraduate years. I would also like to thank Dr. Hanumolu and Dr. Temes for their education
and insight both in and outside of class.
Many educators taught me the fundamentals that I needed for work and life and deserve
more recognition then they get. Mr. Gary Peterson taught me the value of self-learning, went
out of his way to find resources that fit my more unconventional learning styles as a child, and
took the time to talk one-on-one to me about my decisions in ways that influenced my path
years into the future. Barry Creasy helped me understand the value of work and responsibility,
teaching me how to make the most of my time and skills in the real world as a middle schooler.
Dave Thom introduced me to the world of electronics without ever touching a calculus equation
and created the foundation for how I look at the electronic world. Even during my junior and
senior years of undergrad, I would see things I had learned in his high school classes and wish he
was in the room to show everyone (and me again) how to conceptualize the fundamental
concepts being taught before me though a pile of equations.
This research work would definitely not be possible without my family and friends that have
supported me thought my life as well. My parents were very intentional about encouraging and
teaching me. As a child, they were the one quizzing me on social studies, schlepping me to a
plethora of clubs, and even watching Jeopardy with me when I’m sure they had something
better to do. My brother Monte also influenced where I am today and was a great teacher and
protector in my younger years. I often paved my path based on the successes and troubles I
watched my brother go though both in school and life, and still appreciate him saving a seat on
the bus for me in elementary school. My friends have been critical to molding me into the right
direction as well. Aaron Harada invested much of his time into my life and was really the one
who kept me going to church and connected with God in the early years of my faith, even when
I was tempted to stray away. He and Bangda Yang were great roommates as well though the
early years of college. Too many others to mention also guided me and the thesis would be too
long if they were listed.
My wife and love Shannon deserves to be thanked as she was a great support thought the
whole grad school experience, patiently letting me vent, not being afraid to correct me and
sometimes laughing at my puns. Hopefully we can now make up for all the time lost to late
nights in the lab, trips to Corvallis, and unexpected simulation running.
Finally, I thank God for salvation and making my life better then I deserve so far.
TABLE OF CONTENTS
Page
1. INTRODUCTION .................................................................................................. 1
2. THE SAR ADC ...................................................................................................... 3
2.1 ANALOG TO DIGITAL CONVERSION .......................................................................................... 3
1.1.1 ADC Specifications ................................................................................................................. 3
1.1.2 ADC Varieties......................................................................................................................... 7
2.2 SUCCESSIVE APPROXIMATION CONVERTERS ............................................................................ 10
2.2.1 The Successive Approximation Algorithm ............................................................................... 10
2.2.2 Electrical Successive Approximation ....................................................................................... 12
2.2.3 Historical SAR Varieties and SAR Prior Art ............................................................................... 13
2.3 THE MCS SAR ................................................................................................................... 18
2.3.1 MCS SAR Operation ................................................................................................................. 18
2.3.2 MCS SAR Block Level Structure – Capacitor Array .............................................................. 20
2.3.3 MCS SAR Block Level Structure – DAC Drivers ......................................................................... 24
2.3.4 MCS SAR Block Level Structure – Quantizer ............................................................................ 28
2.3.5 MCS SAR Block Level Structure – SAR Logic ............................................................................ 29
2.4 SAR ADC TRENDS AND INNOVATIONS ................................................................................... 30
1.3.1 SAR ADC Trends................................................................................................................... 31
1.3.2 Recent and Relevant SAR Innovations: The Asynchronous SAR ......................................... 33
1.3.3 Recent and Relevant SAR Innovations: SAR Energy Reduction ........................................... 35
1.3.3 Recent and Relevant SAR Innovations: SAR Redundancy ................................................... 36
3. THE TERNARY SAR ............................................................................................ 39
3.1 MODERN SAR LIMITATIONS ................................................................................................. 39
3.1.1 The MCS SAR ........................................................................................................................... 39
3.1.2 SAR Innovations ....................................................................................................................... 39
3.2 THE TERNARY SAR STRUCTURE ............................................................................................. 41
3.2.1 SAR Comparator Delay ............................................................................................................ 42
3.2.2 Ternary Structure .................................................................................................................... 43
3.3 TSAR INHERENT BENEFITS ................................................................................................... 45
3.3.1 TSAR Redundancy .................................................................................................................... 45
TABLE OF CONTENTS (Continued)
Page

3.3.2 Speed Improvements .............................................................................................................. 46
3.3.3 DAC Activity Reduction ............................................................................................................ 46
3.3.4 Residue Shaping ...................................................................................................................... 47
3.4 TSAR STRUCTURAL ENHANCEMENTS ..................................................................................... 50
3.4.1 Reference Grouping................................................................................................................. 50
3.4.2 Time Reference Calibration ..................................................................................................... 52
3.4.3 TSAR Overall Power Savings .................................................................................................... 53
3.5 CMOS CIRCUIT IMPLEMENTATION ........................................................................................ 54
3.5.1 Quantizer Implementation ...................................................................................................... 55
3.5.2 Logic Implementation .............................................................................................................. 58
3.5.3 DAC and Driver Implementation ............................................................................................. 62
3.5.4 Interface Circuitry .................................................................................................................... 64
3.5.5 Calibration Implementation .................................................................................................... 66
3.6 PHYSICAL DESIGN ............................................................................................................... 68
3.6.1 Top level Floorplan and Chip ................................................................................................... 68
3.6.2 Quantizer Layout ..................................................................................................................... 71
3.6.3 DAC and Logic Layout .............................................................................................................. 72
3.6.4 Interface Circuitry Layout and Placement ............................................................................... 74
3.7 TEST SETUP AND MEASURED RESULTS ................................................................................... 75
3.7.1 Test and Measurement Setup ................................................................................................. 75
3.7.2 Measurement Results: Accuracy ............................................................................................. 77
3.7.3 Measurement Results: Power ................................................................................................. 78
3.7.4 Results Comparison ................................................................................................................. 80
3.8 TSAR CONCLUSIONS ........................................................................................................... 81
3.9 ACKNOWLEDGEMENTS ........................................................................................................ 81
4. RESIDUE SHAPING ............................................................................................ 82
4.1 MULTI-STAGE ADC REDUNDANCY ........................................................................................ 82
4.1.1 Half-bit Redundancy ................................................................................................................ 83
4.1.2 CRZ Redundancy ...................................................................................................................... 84
4.1.3 Sub-Radix Redundancy ............................................................................................................ 85
4.1.4 Extra Stage Redundancy .......................................................................................................... 86
4.2 IDEAL RESIDUE SHAPING ...................................................................................................... 86
4.2.1 Residue Shaping in a 1.5b/stage Pipeline ADC ........................................................................ 87
4.2.2 Higher Order Half-Bit Redundant Residue Shaping ................................................................. 90
4.2.3 Ideal Back-End ADC Design ...................................................................................................... 91
4.2.4 Shifted Back-End ADCs ............................................................................................................ 93
4.2.5 Extra Cycle, Sub-Radix, and CRZ Stage Shaping ....................................................................... 94
4.3 RESIDUE SHAPING RESPONSE TO NON-IDEALITIES .................................................................... 95
TABLE OF CONTENTS (Continued)
Page

4.3.1 Analysis of Offsets in Residue Shaping .................................................................................... 96
4.3.2 ADC Design for Optimized PDF Residue Shaping ..................................................................... 99
4.3.3 Modification to CRZ ADCs for PDF Residue Shaping.............................................................. 102
4.4 RESIDUE SHAPING CONCLUSION .......................................................................................... 105
4.5 RESIDUE SHAPING ACKNOWLEDGEMENTS ............................................................................. 105
5. THE EMCS SAR ............................................................................................... 106
5.1 REVIEW OF THE MCS SAR DAC SWITCHING ......................................................................... 106
5.2 THE EARLY RESET MCS SAR .............................................................................................. 109
5.3 EMCS IMPLEMENTATION .................................................................................................. 114
5.4 EMCS CONCLUSIONS ........................................................................................................ 116
5.5 EMCS ACKNOWLEDGEMENTS ............................................................................................ 116
6. THE FEEDBACK INITIALIZED TERNARY SAR .................................................... 117
6.1 TERNARY SAR LIMITATIONS ............................................................................................... 117
6.1.1 TSAR Windowing ................................................................................................................... 118
6.1.2 Cyclical Switching................................................................................................................... 119
6.1.3 Comparator Accuracy Requirements .................................................................................... 119
6.2 THE FEEDBACK INITIALIZED TERNARY SAR ............................................................................ 120
6.2.1 FITSAR Nesting ....................................................................................................................... 121
6.2.2 Coarse/Fine Digital Recoding ................................................................................................. 122
6.2.3 Feedback Initialization ........................................................................................................... 123
6.3 FITSAR STRUCTURAL ENHANCEMENTS ................................................................................ 126
6.3.1 Redundancy, Grouping, and Residue Shaping ....................................................................... 126
6.3.2 Coarse ADC Optimization ...................................................................................................... 128
6.3.3 C-R2R DAC Optimization ........................................................................................................ 129
6.4 CMOS CIRCUIT IMPLEMENTATION ...................................................................................... 131
6.4.1 Quantizer Design ................................................................................................................... 132
6.4.2 Coarse and Fine Logic (Handoff from coarse and fine, ref buffer) ........................................ 134
6.4.3 Internal and External Clock Buffer Design ............................................................................. 136
6.5 PHYSICAL DESIGN ............................................................................................................. 138
6.5.1 Top Level Floorplan ............................................................................................................... 138
6.5.2 Quantizer Layout ................................................................................................................... 140
6.5.3 Coarse and Fine DAC ............................................................................................................. 142
6.6 TEST SETUP AND MEASURED RESULTS ................................................................................. 144
6.7 FITSAR CONCLUSIONS ...................................................................................................... 145
6.8 ACKNOWLEDGEMENTS ...................................................................................................... 146
7. THE TERNARY R2R DAC .................................................................................. 147