The Processor: Datapath and Control

113 Pages·2005·1.9 MB·English

by  Atlantis Sjerry

D
e
p
t
.

E
l
e
c
t
r
o
n
i
c
s

E
n DEE 1053 Computer Organization
g
i
n
e
e Lecture 5: The Processor: Datapath and
r
i
n
g
, Control
N
a
t
i
o
n
a
l

C
h
i
a
o
Dr. Tian-Sheuan Chang
T
u
n
[email protected]
g

U
Dept. Electronics Engineering
n
i
v
e National Chiao-Tung University
r
s
i
t
y
Outline
• Logic Design Conventions
I
n
s
t • Basic MIPS implementation
i
t
u
t
e

o • Building a Datapath
f

E
l
e
c • Simple Implementation
t
r
o
n
i
c
• Multicycle Implementation
s
,
N
a
t • Exceptions
i
o
n
a
l • Microprogramming for control design
C
h
i
a
o

T
u
n
g

U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor 1
Logic Design Conventions
• Two types of logic elements
I
n
s
– Combinational logic
t
i
t
u
t
e • Output only depends on the current input

o
f

E • Uses for ALU, multiplier, and other datapath
l
e
c
t
r – Sequential logic
o
n
i
c
s • Output depends on current inputs and current states
,
N
a • State element to store the states
t
i
o
n
a
l

C
h
i
a
o

T
u
n
g

U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor 2
Logic Design Convention: State Elements
• Two styles
I – Unclocked vs. Clocked
n
s
t
i – Clocks used in synchronous logic
t
u
t
e • when should an element that contains state be updated?

o
f • Depends on the element type
E
l
e
• Two synchronous state elements
c
t
r
o
n – Latch
i
c
s • State changes on the valid level (level-triggered)
,
N
– D Flip Flops
a
t
i
o • state changes only on a clock edge (edge-triggered methodology)
n
a
l

C
h
i
a Falling edge
o
T cycle time
u
n
g

U
n
i
v
e
r
s
Clock period Rising edge
i
t
y
DEE 1050 Lecture 5: Processor
Clocking Methodology
• Clocking methodology
I – Defines when signals can be read and when they can be written
n
s
t
i – Mainstream: An edge triggered methodology
t
u
t
e • Determine when data is valid and stable relative to the clock

o
f • Typical execution:
E
l
e
c – read contents of some state elements,
t
r
o
– send values through some combinational logic
n
i
c
s – write results to one or more state elements
,
N
a
State State
t
io element Combinational logic element
n 1 2
a
l

C
h
i
a
o

T
u
Clock cycle
n
g

U
n
i
v
e
r Clock + write control signals
s
i
t
y
DEE 1050 Lecture 5: Processor
Read/Write at the Same Cycle
• Use the edge-triggered methodology
I
n
s
– Read at the first half cycle and write at the second half
t
i
t
u
t
e cycle

o
f

E
l
e
c
t
r
o
n
i
c
s
,
N
a
t
i
o
n
a
l

C
h
i
a
o

T
u
n
g

U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor 5
Register File
Read register
• Built using D flip-flops
number 1
I
n Register 0
s
t
it Register 1
u M
t
e
. . . u Read data 1

o
f x
E Read register Register n – 2
l
e number 1
Read
c Register n – 1
t data 1
r Read register
o
n number 2
i
c
Register file
s Read register
, Write Read
N register data 2 number 2
a
t Write
i
o data Write
n
a M
l
C u Read data 2
h x
i
a
o

T
u
n
g

U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor
Abstraction
• Make sure you understand the abstractions!
I
n
s
t • Sometimes it is easy to think you do, when you
i
t
u
t
e
don’t
o
f

E
l
e Select
c
t
r
o
n A31
i M
c
s Select u C31
,
x
N B31
a
32
t A
i M
o
32
n u C A30
a 32 x M
l B u C30

C B30 x ...
h
i ..
a .
o

T A0
u M
n u C0
g x
B0
U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor 7
Register File
• Note: we still use the real clock to determine
I
n
s when to write
t
i
t
u
t
e
o Write
f

E
l
e C
c 0
t
r Register 0
o 1
nic Register number n-to-2n ... D
s decoder
, C
N
Register 1
a n – 1
t
i D
o n
n
a
.
l C ..
h
i
a
o
C

T
Register n – 2
u
n
D
g

U
C
n
i Register n – 1
v
e
r Register data D
s
i
t
y
DEE 1050 Lecture 5: Processor
Outline
• Logic Design Conventions
I
n
s
t • Basic MIPS implementation
i
t
u
t
e

o • Building a Datapath
f

E
l
e
c • Simple Implementation
t
r
o
n
i
c
• Multicycle Implementation
s
,
N
a
t • Exceptions
i
o
n
a
l • Microprogramming for control design
C
h
i
a
o

T
u
n
g

U
n
i
v
e
r
s
i
t
y
DEE 1050 Lecture 5: Processor 9