The Final Word on the 8051 Microcontroller (tutorial)

255 Pages·1994·1.479 MB·English

by  M. Chapman

THE FINAL WORD ON THE 8051
- Introduction
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If you have a C compiler for the 8051, then I congratulate you. You have made an excellent decision in
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excellent decision in 8051 development tools. I have found that the Keil package for the 8051 provides
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egaP 1
CHAPTER 2 - THE HARDWARE
- The Hardware
Overview
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control systems. It is used in a wide variety of applications from military equipment to automobiles to the
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family of microcontrollers is available in a wide array of variations from manufacturers such as Intel ,
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2
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developers will only have to learn this one platform.
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egaP 2
THE FINAL WORD ON THE 8051
Memory Organization
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The CODE Space
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over an in circuit emulator which is usually a rare commodity.
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egaP 3
CHAPTER 2 - THE HARDWARE
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egaP 4
THE FINAL WORD ON THE 8051
The DATA Space
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with care, however, due to the limited amount of memory in this segment.
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.ec aA pTensAhiDt
Special Function Registers
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+ 0 1 2 3 4 5 6 7
e rsaretsiger
F8
doestrarefer
F0 B
special function
E8
sretsiger ro(RFS s E0 ACC
for short). Many of D8
them are bit D0 PSW
e. heTlbasserdda C8 T2CON RCAP2L RCAP2H TL2 TH2
bits in the bit C0
sR FeSlbasserdda B8 IP
reebh tniaec B0 P3
,em a yndbessecca A8 IE
.sse r xdtrediodabni A0 P2
re fnu,eaosrcyuhT 98 SCON SBUF
to the EA bit of the 90 P1
e ltbpaunrEretnI 88 TCON TMOD TL0 TL1 TH0 TH1
RFS sa , A,E7.EIro 80 P0 SP DPL DPH PCON
.Hs FReAFh0ST
hc ussgni hltortnoc - Denotes bit addressable Special Function Registers in this table and all following diagrams
as the function of
elbaT A - 1
the timer ,sretnuoc/
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egaP 5
CHAPTER 2 - THE HARDWARE
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The IDATA Space
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The XDATA Space
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minimum of one cycle in addition to the two cycles imposed by the memory access itself. Therefore, it is
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egaP 6
THE FINAL WORD ON THE 8051
Bit processing and Boolean logic
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gnitsi LA - 1
MOV C, 22H ; move the bit value at address
; 22H to the carry bit
ORL C, 23H ; or the bit value a t address
; 23H into the carry bit
ANL 24H, C ; and the carry bit into bit
; address 24H
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set, but could not wait indefinitely. This routine would have to decrement a timeout value and exit the
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and exit the polling loop. With normal logic flow, the routine would look like the following.
gnitsi LA - 2
MOV timeout, #TO_VAL ; set the timeout value
L2: JB P0.0, L1 ; check the bit
DJNZ timeout, L2 ; decrement the timeout counter
; and sample aga in
L1: CLR P0.0 ; force P0.0 to logic level 0
RET ; exit the routine
noitcurt sCegnBhniJtisU .swoll osdfaed oedcblu oewnitu oerm ae sh,t
gnitsi LA - 3
MOV timeout, #TO_VAL ; set the timeout value
L2: JBC P0.0, L1 ; check the bit and force P0.0
; to logic level 0 if set
DJNZ timeout, L2 ; decrement the timeout counter
L1: RET ; exit the routine
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egaP 7
CHAPTER 2 - THE HARDWARE
Addressing Modes
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.wole bnwoh ser asessecca
gnitsi LA - 4
MOV A, 03H ; move the value at address 03H to
; the accumulator
MOV 43H, 22H ; move the value at address 22H to
; address 43H
MOV 02H, C ; move the value of the carry bit to
; bit address 02H
MOV 42H, #18 ; load address 42H with the value 18
MOV 09H, SBUF ; load the value in SBUF into
; address 09H
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directly.
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RTPD or the PC register and an offset in the accumulator. This is useful for operations involving lookup
selbat .wo lnew boeshresasse cycrao mtecmer i sdfen oli.pm axE
egaP 8
THE FINAL WORD ON THE 8051
gnitsi LA - 5
DATA and IDATA accesses
MOV R1, #22H ; set R1 to point at DATA
; address 22H
MOV R0, #0A9H ; set R0 to point at IDATA
; address A9H
MOV A, @R1 ; read the value at DATA
; address 22H
; into the accumulator
MOV @R0, A ; write the value in the accumulator
; to IDATA address A9H
INC R0 ; set R0 to point at IDATA
; address AAH
INC R1 ; set R1 to point at DATA
; address 23H
MOV 34H, @R0 ; write the value at IDATA
; address AA
; to DATA address 34H
MOV @R1, #67H ; write 67H to DATA addre ss 23H
XDATA accesses
MOV DPTR, #3048H ; set DPTR to point at XDATA
; address 3048H
MOVX A, @DPTR ; read the data at XDATA
; address 3048H
; into the accumulator
INC DPTR ; set DPTR to point at XDATA
; address 3049H
MOV A, #26H ; set the accumulator to 26H
MOVX @DPTR, A ; write 26H to XDATA address 3049H
MOV R0, #87H ; set R0 to point at XDATA
; address 87H
MOVX A, @R0 ; read the data at XDATA
; address 87H into the accumulator
CODE accesses
MOV DPT R, #TABLE_BASE ; set DPTR to point at the base
; of a lookup table
MOV A, index ; load the accumulator with an
; index into the table
MOVC A, @A+DPTR ; read the value from the table
; into the accumulator
egaP 9
CHAPTER 2 - THE HARDWARE
Processor Status
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y trsi o nryty yei arar ,rhahtprla,trttciaui sian ibcmlennbc oshuihao dciwcxtihecut tsAaaDiurCweBpo
ekso snatruaebtsi g eethrcte lhecs ish t wo idw,bntsag aelsfop rluapre n oe,wggt awloflfr e dvgnoaalf
.ethltuafe d d ,esenArooi ftreenehb ettnm sokiing taescbrteil beeskam a owt t irbeb mmuonrf 0 ot3
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. .wtn o uonf lW oiwoeSesytobPhiachT les klrneeastbs ieghetr
Power Control
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NO Ce Pha tidvessec ce arsaed oe ms.e ehd Tonmw ordew od pnead oemldi lort NrOeCw oP( ) SFR
n inwoh ss ihcihw elbaT A -2 . The idle mode is activated by setting the IDLE bit high. The idle mode
seunit nrooctalli ceddshneotavres eesrrtpanet nMloAa cRn. rp ne oootttinstIuc emxaerg olsrlepasuac
ot nur tub si dekcolb morf eht .UPC ehT sremit dna eht TRA Ueunitnoc ot noitcnuf sa .lamron eldIedom
is terminated by the activation of any interrupt. Upon completion of the interrupt service routine,
noitucexe lliw eunitnoc morf eht noitcurtsni gniwollof eht noitcurtsni hcihw tes eht ELDI.tib
PPrroocceessssoorr SSttaattuuss WWoorrdd ((PPSSWW)) -- BBiitt AAddddrreessssaabbllee
CY AC F0 RS1 RS0 OV USR P
CY Carry Flag
AC Auxiliary Carry Flag
F0 General Purpose Flag
RS1 Register Bank Selector 1. MSB of selector.
RS0 Register Bank Selector 0. LSB of selector.
OV Overflow Flag
USR User Definable Flag
P Accumulator Parity Flag
elbaT A - 2
ed onmw ordew oephT is activated by setting the PDWN bit high. In this mode, the on chip oscillator is
sg.aan doselAtl ae hrnaoituce xeerawtf oslsal esTwaR Ae Uhd tnsarem ie th, ts.u dheTppots
minimum of 2 volts are applied to the chip (assuming a five volt part) the contents of the internal RAM
re w goanpiylp pyseabid onmw ordew oft pouroosseco re phetcr ooy ftay wl .ne doheTvrese relpbliw
.tes enro
ehTDOMS (Serial MODe detaren ergehte htwr olpair ee shfstoet adru ae bhetlbu ooddte sen ubat ci)b
yb eht remit 1 wolfrev oetar ro e hr to.tyaclnleiucqseorf gnitteS DOMS hgih sesuac a gnilbuod foeht
,se td auerat b ae ,dr d,n r 1eero 2ide.tn omo2em3aesnt sirgie uTehn pWeTo h R ewrAeh oUttdfaurab
the value of SMOD will have no effect on the UART.
egaP 01