The design of a programmable convolutional encoder using VHDL and an FPGA

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by  Snelgrove, Andrew H.

Approved for public release; distribution is unlimited.
THE DESIGN OF A PROGRAMMABLE CONVOLUTIONAL
ENCODER USING VHDL AND AN FPGA
by
Andrew H. Snelgrove
Naval Air Warfare Center - Weapons Division
B.S., Rensselaer Polytechnic Institute, 1986
Submitted in partial fulfillment ofthe
requirements for the degree of
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
from the
NAVAL POSTGRADUATE SCHOOL
December 1994-
S
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Naval Postgraduate School ECE Naval Postgraduate School
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11.TITLE(IncludeSecurityClassification)
THE DESIGN OF A PROGRAMMABLE CONVOLUTIONAL ENCODER
USING VHDL AND AN FPGA
12 PERSONALAUTHOR(S)
Snelgrove, Andrew H
13a TYPEOFREPORT 13b TIMECOVERED 14 DATEOFREPORTCYear.Month.Day) 15 PAGECOUNT
Masters Thesis FROM TO December 1994 120
16 SUPPLEMENTARYNOTATION
The views expressed in this thesis are those ofthe author and do not reflect the official policy or position of
the Department ofDefense or the U.S. Government.
17 COSAT1CODES 18 SUBJECTTERMS(Continueonreverseifnecessaryandidentifybyblocknumber)
FIELD GROUP SUB-GROUP
Convolutional encoding, VHDL, FPGA, top-down design, one-hot state
assignment
19 ABSTRACT(Continueonreverseifnecessaryandidentifybyblocknumber)
ConvolutionalencodingisaForwardErrorCorrection(FEC)techniqueusedincontinuousone-wayandrealtimecommunicationlinks Itcanprovidesubstantial improvementinbiterror
rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices This thesis documents the development ofa
programmableconvolutionalencoderimplementedina FieldProgrammableGateArray(FPGA)fromXilinx,Inc.,calledtheXC3064LogicCellArray(LCA) Theencoderiscapableofcodinga
digital datastreamwith anyone of39 convolutional codes Because the LCA isusedforthe hardware implementation, the design can be changed orexpanded conveniently in the lab In
particularlyflexible systems, several encoderdesigns can be stored inthe systemRAM eachone beingdownloadedintotheLCA underdifferent circumstances The encoderhasa simple
microprocessor interface, aregisterfile forstorage ofcodeparameters, a test circuit, and amaximumbitrate ofabout 15 Mbits/s Special design techniques like one-hot state assignment,
pipelining,andtheuseofredundantstatesareemployedtotailorthehardwaretotheLCAarchitecture Otherwaystoimprovetheoutputbitratearesuggested TheVHSICHardwareDescription
Language(VHDL)isusedtomodelabstractbehaviorandtodefinerelationshipsbetweenbuildingblocksbeforethehardwareimplementationphase
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ABSTRACT
Convolutional encoding is a Forward Error Correction (FEC) technique used in
continuous one-way and real time communication links. It can provide substantial
improvement in bit error rates so that small, low power, inexpensive transmitters can be
used in such applications as satellites and hand-held communication devices. This thesis
documents the development of a programmable convolutional encoder implemented in a
Field Programmable Gate Array (FPGA) from Xilinx, Inc., called the XC3064 Logic Cell
Array (LCA). The encoder is capable of coding a digital data stream with any one of 39
convolutional codes. Because the LCA is used for the hardware implementation, the design
can be changed or expanded conveniently in the lab. In particularly flexible systems, several
encoder designs can be stored in the system RAM, each one being downloaded into the
LCA under different circumstances. The encoder has a simple microprocessor interface, a
register file for storage ofcode parameters, a test circuit, and a maximum bit rate ofabout
15 Mbits/s. Special design techniques like one-hot state assignment, pipelining, and the use
of redundant states are employed to tailor the hardware to the LCA architecture. Other
ways to improve the output bit rate are suggested. The VHSIC Hardware Description
Language (VHDL) is used to model abstract behavior and to define relationships between
building blocks before the hardware implementation phase.
111
TABLE OF CONTENTS
INTRODUCTION
I. 1
CONVOLUTIONAL ENCODING
n. 3
INTRODUCTION
A. 3
B. CONVOLUTIONAL CODES 4
C. ENCODERS 4
CONNECTION VECTORS
D. 5
E. CODING GAIN 6
III. ENCODER DESIGN DETAILS 9
A. TOP-DOWN DESIGN 9
B. TOP-LEVEL OVERVIEW 10
DATAPATH
C. 11
MUX
1. 12
2. SHIFTREG 12
DATAREG
3. 12
GENERATOR
4. 13
REGFILE
5. 13
CONTROL
D. 14
LOADER
1. 15
INENBLE
2. 16
SEQUENCER
3. 17
4. TEST 18
OPERATION
E. 18
F. INTERFACE 20
IV