The Complete Verilog Book

471 Pages·2002·6.568 MB·English

by  Vivek Sagdeo (auth.)

THE COMPLETE VERILOG BOOK
THE COMPLETE VERILOG BOOK
by
Vivek Sagdeo
Sun Micro Systems, Inc.
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
CD-ROM available only in print edition.
eBookISBN: 0-306-47658-4
Print ISBN: 0-7923-8188-2
©2002 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©1998 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstore at: http://ebooks.kluweronline.com
To
My Parents,
Sons-Parth and Nakul,
Anjali,
Friends
LIST OF FIGURES
Figure 1-1. Block Diagram of a System with Processor, Main Memory, and Cache 8
Figure 1-2. Bottom-up Methodology and Verilog Language Features Support 14
Figure 1-3. Top-Down Methodology and Equivalent Verilog Language
Features Support 14
Figure 1-4. Typical Design Flow with Verilog 15
Figure 1-5. Verilog Keywords 17
Figure 2-1. Tables of Net Types and Resolution Functions 25
Figure 3-1. Tables of Operators in Verilog Used for Evaluating Expressions 45
Figure 3-2. Schematics for the Adder in Example 3-28 64
Figure 3-3. Top Level Block Diagram of r4200 68
Figure 3-4. UltraSPARC-IIi Block Diagram 82
Figure 4-1. Schematics for Example 4-1 86
Figure 4-2. Network Data Structure for the andor Verilog Model in Example 4-1 91
Figure 4-3. Schedule of Events for a Verilog Model 93
Figure 4-4. Algorithm for Verilog Model Execution 93
Figure 4-5. Algorithm for Processing an Event 94
Figure 4-6. Order of Events at a Time and Event Structure Diagrams 94
Figure 4-7. Algorithm for Scheduling an Event 95
Figure 6-1. Tables for Each Built-in Gate in Verilog 136
Figure 11-1. State Diagram for Cache Controller with Write-Back Policy 217
Figure 11-2. Block Diagram for the Cache Controller with Write-Back Policy
Containing Dirty Bits 222
Figure 11-3. State Transition Diagram for the Cache Controller with
Write-Back Policy 223
Figure 11-4. Block Diagram for a Cache System 230
Figure 12-1. Typical Design Flow with Verilog IncludingSynthesis 245
Figure 12-2. Logic Synthesis Components of Verilog Based Synthesis 246
Figure 12-3. Components of Behavioral Synthesis with Verilog 247
Figure 12-4. Traditional View (Class A or Mealy Machine) of a Sequential Design 248
Figure 12-5. Modern View (Class A – Sagdeo Machine) of a Sequential Design 248
Figure 14-1. Sharings Adders Amongst Different Operations in Example14-1 291
Figure 16-1. C Interface Components for Verilog HDL 313
Figure 17-1. Schematics for a Static RAM Cell with Bidirectionals and Strengths 317
PREFACE
The Verilog hardware description language (HDL) provides the ability to
describe digital and analog systems. This ability spans the range from
descriptions that express conceptual and architectural design to detailed
descriptions of implementations in gates and transistors. Verilog was
developed originally at Gateway Design Automation Corporation during the
mid-eighties. Tools to verify designs expressed in Verilog were implemented
at the same time and marketed. Now Verilog is an open standard of IEEE
with the number 1364. Verilog HDL is now used universally for digital
designs in ASIC, FPGA, microprocessor, DSP and many other kinds of
design-centers and is supported by most of the EDA companies. The
research and education that is conducted in many universities is also using
Verilog. This book introduces the Verilog hardware description language and
describes it in a comprehensive manner.
Verilog HDL was originally developed and specified with the intent of use
with a simulator. Semantics of the language had not been fully described
until now. In this book, each feature of the language is described using
semantic introduction, syntax and examples. Chapter 4 leads to the full
semantics of the language by providing definitions of terms, and explaining
data structures and algorithms.
The book is written with the approach that Verilog is not only a simulation
or synthesis language, or a formal method of describing design, but a
complete language addressing all of these aspects. This book covers many
aspects of Verilog HDL that are essential parts of any design process. It has
the view of original development, and also encompasses changes and
additions in subsequent revisions. The book starts with a tutorial
introduction in chapter 1, then explains the data types of Verilog HDL in
chapter2. Today´s object-orientedworldknowsthatthelanguage-constructs
and data-types are equally important parts of a programming language.
Chapter 3 explains the three views of a design object: behavioral, RTL and
structural. Each view is then described in detail, including the semantic
introduction, example and syntax for each feature, in chapters 3, 5 and 6.
Verilog takes the divide and conquer approach to the language design by
separating various types of constructs using different syntax and semantics.
The syntax and semantics include features to describe design using the three
levels of abstractions, features for simulation control and debug, preprocessor
features, timing descriptions, programming language interface and
miscellaneous system tasks and functions.
System tasks and functions that are useful for non-design descriptions, such
as input-output, are described in chapters 8 and 10. The preprocessor enables
one to define text substitutions and to include files, which are defined in
chapter 9. The building of systems using all features is explained in chapter
11. Synthesis is an essential part of today´s design process, and Verilog HDL
usage for synthesis requires special language understanding. The
understanding needed is provided in chapters 11 to 13. Timing descriptions
form a separate class of features in Verilog and are described in chapter 15.
Chapter 17 describes how programming language interface (PLI) provides
access to Verilog data structures and simulation information via common
data definitions and routines. Standard Delay Format, which is discussed in
chapter 18, extends capabilities of timing descriptions of specific blocks in
Verilog, and is used in ASIC designs extensively. Chapter 19 enunciates the
analog extensions to Verilog in the form of Verilog-A and Verilog-MS.
Simulation speed is an important part of Verilog HDL usage, and a large part
of the design cycle is spent in design verification and simulation. Some
techniques to enhance this speed are discussed in chapter 20.
The book keeps the reader abreast of current developments in the Verilog
world, such as Verilog-A, cycle simulation, SDF, DCL and uses IEEE 1364
syntax.
I hope that this book will be useful to all of those who are new to Verilog
HDL, to those who want to learn additional facets, and to those who would
like a reference book during the development of a hardware design or
software tool with Verilog HDL. I wish for you to design and implement
some interesting designs of ASICs, FPGAs, microprocessors, caches,
memories, boards, systems and/or tools like simulators, synthesizers, timing
analyzers, formal verifiers with Verilog HDL, and to have a lot of fun doing
so.
-- Vivek Sagdeo
ACKNOWLEDGEMENTS
A book of this size takes many different things to come together . I would like to
acknowledge Carl Harris of Kluwer for encouragement and for facilitating the creation of
manuscript. Jackie Denfeld handled the creation of final manuscript in a short time well. Tedd
Corman provided the editorial review and my experience of working with him in the past on
simulation and HDLs has been valuable. Satish Soman provided feedback from the design
perspective. UC Berkeley extension provided the teaching environment for me that has added
the academic dimension to this book. Dr Richard Tsina, Joan Siau and Roxanne Giovanetti
from UCB deserve mention for their support. Students of the class “Digital Design of Verilog
HDL” from UCB and PerformancAE kept the book-writing interesting and live. My
coworkers from SUN microsystems have been very cooperative and accomodating and have
really good insight into digital design and microprocessors.
While working at Gateway Design where Verilog was designed and implemented, a terrific
team was in place. Prabhu Goel, Barry Rosales, Manoj Gandhi, Phil Moorby, Ronna Alintuck
and many from Marketing and Sales made this work on Verilog and well-rounded.
Over the several years, experiences of working at Gateway(Cadence), Viewlogic, Silicon
Graphics, Meta Software, Philips Semi and SUN Microsystems and IEEE 1364 have provided
the background to cover many aspects of Verilog including language, digital and analog,
system and microprocessors and have given a perspective that has made this work possible.
I acknowledge all those whose names can’t be mentioned for lack of space but have been part
of various projects with me.
DISCLAIMER
This DISK (CD ROM) is distributed by Kluwer Academic
Publishers with *ABSOLUTELY NO SUPPORT* and *NO
WARRANTY* from Kluwer Academic Publishers.
Use or reproduction of the information provided on this DISK (CD
ROM) for commercial gain is strictly prohibited. Explicit
permission is given for the reproduction and use of this
information in an instructional setting provided proper reference is
given to the original source.
KluwerAcademic Publishers shall not be liable for damage in
connection with, or arising out of, the furnishing, performance or
use of this DISK (CD ROM).
TABLE OF CONTENTS
1. INTRODUCTION TO VERILOG HDL 1
1.1 Language Motivation 1
1.1.1 Language Design 1
1.1.2 Verilog World 1
1.1.3 Accessory Specifications 2
1.2 Tutorial Via Examples 2
1.2.1 Counter Design 2
1.2.2 Factorial Generator 7
1.2.3 System Design withProcessor, Memory, and Cache 8
1.2.4 Cache System - Behavioral Model 10
1.3 Overview of Verilog HDL 13
1.3.1 Correspondence To Digital Hardware 13
1.3.2 Typical Design Flow withVerilog 15
1.3.3 List of Keywords 17
1.3.4 Comment Syntax 17
1.4 Syntax Conventions 18
1.5 Exercises 19
2. DATA TYPES IN VERILOG 21
2.1 Overview 21
2.2 Value Systems 21
2.3 Data Declarations 22
2.3.1 Introduction 22
2.3.2 Examples 23
2.3.3 Syntax 23
2.4 Reg Declaration 23
2.4.1 Introduction 23
2.4.2 Examples 24
2.4.3 Syntax 24
2.5 Net Declaration 24
2.5.1 Introduction 24
2.5.2 Syntax 28
2.5.3 Examples 29
2.6 Port Types 29
2.6.1 Introduction 29
2.6.2 Examples 30
2.6.3 Syntax 30
2.7 Aggregates – 1 and 2 Dimensional Arrays (Vectors and Memories) 31
2.7.1 Introduction 31
2.7.2 Examples 31
2.7.3 Syntax 32