The Bounding Approach to VLSI Circuit Simulation

231 Pages·1986·13.088 MB·English

by  Charles A. Zukowski (auth.)

THE BOUNDING APPROACH TO
VLSI CIRCUIT SIMULATION
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
Other books in the series:
Logic Minimization Algorithms for VLSI Synthesis. R.K. Brayton,
G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincentelli.
ISBN 0-89838-164-9.
Adaptive Filters: Structures, Algorithms, and Applications.
M.L. Honig and D.G. Messerschmitt. ISBN 0-89838-163-0.
Computer-Aided Design and VLSI Device Development. K.M. Cham,
S.-Y. Oh, D. Chin and J.L. Moll. ISBN 0-89838-204-1.
Introduction to VLSI Silicon Devices: Physics, Technology and
Characterization. B. EI-Kareh and R.J. Bombard. ISBN 0-89838-210-6.
Latchup in CMOS Technology: The Problem and Its Cure.
R.R. Troutman. ISBN 0-89838-215-7.
Digital CMOS Circuit Design. M. Annaratone. ISBN 0-89838-224-6.
THE BOUNDING APPROACH TO
VLSI CIRCUIT SIMULATION
by
Charles A. Zukowski
Columbia University
New York
.,
~
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
Zukowski, Charles A.
The bounding approach to VLSI circuit simulation.
(The Kluwer international series in engineering and
computer science. VLSI, computer architecture, and
digital signal processing)
Bibliography: p.
Includes index.
1. Integrated circuits-Very large scale
integration-Mathematical models. 2. Integrated
circuits-Very large scale integration-Data processing.
I. Title. II. Series.
TK7874.Z85 1986 621.395 86-10925
ISBN 978-1-4684-9893-6 ISBN 978-1-4684-9891-2 (eBook)
DOI 10.1007/978-1-4684-9891-2
Copyright © 1986 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1986
Softcover reprint of the hardcover 1s t edition 1986
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise,
without the prior written permission of the publisher, Springer Science+Business Media, LLC.
Contents
List of Figures ix
Preface xiii
1. INTRODUCTION 1
2. VLSI CIRCUIT SIMULATION 5
2.1 General Circuit Simulators 5
2.2 Digital MOS Circuit Simulators 7
2.3 Trading Accuracy for Speed 10
2.3.1 Approximating Simulators 10
2.3.2 Bounding Approaches 12
3. SIMULATION WITH BOUNDS 15
3.1 Bound Definition 16
3.1.1 Bounding General Subsets 18
3.1.2 Bounding the Excitations 21
3.1.3 Bounding the Models 25
3.1.4 Bounding the Behaviors 26
3.1.5 Forms of Bounds 28
3.2 Basic Strategy 30
3.2.1 Bounding the Behavior of Simple Circuits 31
3.2.2 Bounding the Behavior of Monotonic Subcircuits 32
3.2.3 Relaxation of Bounds 35
3.3 Simulating Various Digital MOS Subcircuits 41
3.3.1 Standard Restoring Logic 41
3.3.2 Pass Logic 43
3.3.3 Latches 44
3.3.4 Ring Oscillators 46
3.3.5 Schmitt Triggers 47
3.3.6 Bootstrap Drivers 49
vi
3.4 Applications for Bounding Algorithms 50
3.4.1 Uncertainty Management 50
3.4.2 Worst Case Analysis 53
3.4.3 Input-Independent Analysis 55
3.5 Summary 58
4. THE VLSI CIRCUIT MODEL 59
4.1 Elements in the VLSI Circuit Model 60
4.1.1 Resistors 60
4.1.2 Transistors 62
4.1.3 Capacitors 65
4.1.4 Element Composition Rules 67
4.2 The Resistor Subnetwork 70
4.2.1 Terminal Contraints 70
4.2.2 Internal Elements 74
4.2.3 One-Port Groups 77
4.2.4 Resistor Subnetwork Summary 82
4.3 The Transistor Subnetwork 84
4.3.1 Comparison with the Resistor Subnetwork 84
4.3.2 Series and Parallel Transistor Compositions 86
4.3.3 Terminal Constraints and Internal Elements 90
4.3.4 Transistor Polarity 94
4.3.5 Transistor Subnetwork Summary 94
4.4 The Capacitor Subnetwork 97
4.4.1 Evaluation of Circuit Dynamics 97
4.4.2 Waveform Relaxation and the Capacitor
Subnetwork 100
4.4.3 Terminal Constraints 107
4.4.4 Internal Elements 109
4.4.5 Capacitor Subnetwork Summary 116
4.5 Node Circuits 117
4.5.1 Single Node Equation 118
4.5.2 Differential Equation Inequalities 119
4.5.3 Monotonicity of the Node Equation 121
4.5.4 Analysis of the Node Equation 124
4.6 Cluster Circuits 125
4.6.1 General Cluster Circuit 126
4.6.2 One-Way Restoring Logic Gate 130
4.6.2.1 Resistive Logic Gate Models 130
4.6.2.2 Interconnect Models 132
4.6.2.3 One-Way Combinational Logic Models 134
4.7 Summary 137
vii
5. BOUND RELAXATION 139
5.1 Theory 140
5.1.1 Definitions 141
5.1.2 Using Bounding Functions to Tighten Bounds 145
5.1.3 Using Bounding Functions to Generate Bounds 146
5.2 D.C. Analysis 149
5.2.1 Basic Strategy 149
5.2.2 Resistor Network Example 150
5.2.3 MOS Feedback Circuit Example 152
5.3 Transient Analysis 154
5.4 Resistive Mesh Circuits 161
5.4.1 Notation and Definitions 163
5.4.2 Bound Relaxation for RC Mesh Circuits 166
5.4.3 Linear RC Mesh Example 170
5.5 Summary 171
6. ALGORITHMS AND EXPERIMENTAL RESULTS 173
6.1 One-Way Logic Gate Models 174
6.1.1 General Logic Gates 175
6.1.2 General Inverters 179
6.1.3 Inverters with Capacitive Loads 181
6.1.4 Experiments 183
6.2 Linear RC Mesh Circuits 186
6.2.1 Bounding Algorithm 187
6.2.2 Experiments 189
6.3 General Circuit Models 194
6.3.1 Partitioning and Scheduling 194
6.3.2 Device Models 196
6.3.3 D.C. Analysis 197
6.3.4 Transient Analysis 198
6.3.5 Experiments 199
6.4 Summary 207
7. CONCLUSION 209
7.1 Future Work 209
7.2 Closing Comments 211
References 212
Index 219
List of Figu res
Figure 2-1: A digital MOS circuit can be partitioned into blocks. 9
Figure 2-2: Two orthogonal approaches to the speed-accuracy 11
tradeoff.
Figure 3-1: Exact and bounding simulators involve mappings 17
between sets.
Figure 3-2: Sets can be bounded using intervals based on a partial 19
ordering.
Figure 3-3: The behavior subset is interpreted through a specification 20
function.
Figure 3-4: Ignoring correlations over time can produce unattainable 25
bounds.
Figure 3-5: Nonmonotonic bounds Can be simplified into monotonic 29
ones.
Figure 3-6: Logic simulation waveforms can be represented with 30
bounds.
Figure 3-7: Simplified circuits are analyzed inside a bounding 31
algorithm.
Figure 3-8: Large MOS circuits can be subdivided into monotonic 33
subcircuits.
Figure 3-9: Simple example of a coupled system. 36
= -
Figure 3-10: Exact relax.ation towards the solution for a 0.5 and 37
a = +0.5.
=
Figure 3-11: Relaxation of bounds for a = - 0.5 and a + 0.5. 38
Figure 3-] 2: Bounding algorithms can analyze restoring logic gates 42
efficiently.
Figure 3-13: Pass networks can contain dynamic storage nodes. 43
Figure 3-14: The behavior of latches can be tightly bounded. 45
Figure 3-15: Ring oscillators restore signals in voltage but not in time. 47
.Figure 3-]6: Schmitt triggers exhibit positive feedback. 48
Figure 3-17: Bootstrap drivers arc sensitive to correlations. 49
Figure 3-18: Simple circuit model to illustrate unceltainty 51
management
Figure 3-] 9: Simple example of a circuit model containing 54
uncertainty.
Figure 3-20: Bounds shrink the search space in input-independent 57
analysis.
x
Figure 4-1: Nonlinear resistors can be bounded with linear ones. 61
Figure 4-2: N-elements and P-eIements are four terminal resistive 63
elements.
Figure 4-3: A physical transistor is modeled using external capacitor 64
elements.
Figure 4-4: Incremental bounds on capacitors limit incremental 66
capacitance.
Figure 4-5: The contribution of each element type is analyzed 68
separately.
Figure 4-6: A CMOS NAND gate partitioned into four element 69
su bnetworks.
Figure 4-7: The resistor subnetwork xR. 71
Figure 4-8: The terminal constraints of XR are monotonic. 73
Figure 4-9: Example of XR with complex dependence on resistor G2. 75
Figure 4-10: All internal nodes of XR are inside one-port groups. 76
Figure 4-11: A simple bridge circuit that is nonmonotonic with 78
respect to RD.
Figure 4-12: Rp contains both linear and nonlinear resistors. 79
Figure 4-13: The operating point lies on the darkened portion of the 80
curve.
Figure 4-14: Branches bo' R1, and R2 form a series-parallel subgroup. 81
Figure 4-15: The n-channel transistor subnetwork 85
}fN'
Figure 4-16: General N-elements model NMOS pullups and 87
transistor groups.
Figure 4-17: Series and parallel connections of general N-elcments. 90
Figure 4-18: The terminal constraints of XN are not necessarily 91
monotonic.
Figure 4-19: A modified circuit can be used to calculate bounds. 92
Figure 4-20: The capacitor subnetwork Xc 98
Figure 4-21: Dataflow diagrams for evaluation of node equations. 100
Figure 4-22: Series combination of capacitors. 105
Figure 4-23: A number of terminal voltages can be solved at once. 110
Figure 4-24: Hounding the effect of internal elements in Xc 112
Figure 4-25: Circuit transformation that can simplify bounding of Xc 113
Figure 4-26: Circuit corresponding to single node equation. 118
Figure 4-27: Circuit corresponding to a typical cluster. 125