Test Pattern Generation using Boolean Proof Engines

195 Pages·2009·4.801 MB·English

by  Rolf Drechsler, Stephan Eggersglüβ, Görschwin Fey, Daniel Tille (auth.)

Test Pattern Generation using Boolean
Proof Engines
Rolf Drechsler (cid:129) Stephan Eggersglüß
Görschwin Fey (cid:129) Daniel Tille
Test Pattern Generation
using Boolean Proof Engines
123
RolfDrechsler GörschwinFey
UniversitätBremen UniversitätBremen
AGRechnerarchitektur AGRechnerarchitektur
Bibliothekstr.1 Bibliothekstr.1
28359Bremen 28359Bremen
Germany Germany
[email protected] [email protected]
StephanEggersglüß DanielTille
UniversitätBremen UniversitätBremen
AGRechnerarchitektur AGRechnerarchitektur
Bibliothekstr.1 Bibliothekstr.1
28359Bremen 28359Bremen
Germany Germany
[email protected] [email protected]
ISBN978-90-481-2359-9 e-ISBN978-90-481-2360-5
DOI10.1007/978-90-481-2360-5
SpringerDordrechtHeidelbergLondonNewYork
LibraryofCongressControlNumber:2009926161
(cid:2)c SpringerScience+BusinessMediaB.V.2009
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Preface
After producing a chip, the functional correctness of the integrated circuit
has to be checked. Otherwise, products with malfunctions would be deliv-
ered to customers, which is not acceptable for any company. During this
post-production test, input stimuli are applied and the correctness of the
output response is monitored. These input stimuli are called test patterns.
ManyalgorithmsforAutomatic Test Pattern Generation(ATPG)havebeen
proposed in the last 30 years. However, due to the ever increasing design
complexity,newtechniqueshavetobedevelopedthatcancopewithtoday’s
circuits.
Classicalapproachesarebasedonbacktrackingoverthecircuitstructure.
They have been continuously improved by using dedicated data structures
and adding more sophisticated techniques like simplification and learning.
Approaches based on Boolean Satisfiability (SAT) have been proposed since
theearly1980s.Comparisonstoother“classical”approachesbasedonFAN,
PODEM and the D-algorithm have shown the robustness and effectiveness
of SAT-based techniques.
Recently, there is a renewed interest in SAT, and many improvements
to proof engines have been proposed. SAT solvers make use of learning and
implication procedures. These new proof techniques led to breakthroughs in
several applications, like formal hardware verification.
In this book, we give an introduction to ATPG. The basic concept and
classicalATPGalgorithmsarereviewed.Then,theformulationofthisprob-
lem as a SAT problem is considered. Modern SAT solvers are explained and
the transformation of ATPG to SAT is discussed. Advanced techniques for
SAT-based ATPG are introduced and evaluated in the context of an in-
dustrial environment. The chapters of the book cover efficient instance gen-
eration, encoding of multiple-valued logic, use of various fault models and
v
vi PREFACE
detailed experiments on multi-million gate designs. The book describes the
state-of-the-art in the field, highlights research aspects and shows directions
for future work.
Bremen, January 2009 Rolf Drechsler
[email protected]
Stephan Eggersglu¨ß
[email protected]
Go¨rschwin Fey
[email protected]
Daniel Tille
[email protected]
Acknowledgments
Parts of this research work were supported by the German Federal Ministry
of Education and Research (BMBF) under the Project MAYA, contract
number 01M3172B, by the German Research Foundation (DFG) under con-
tract number DR 287/15-1 and by the Central Research Promotion (ZF) of
the University of Bremen under contract number 03/107/05. The authors
wish to thank these institutions for their support.
Furthermore, we would like to thank all members of the research group
of Computer Architecture at the University of Bremen, Germany for their
helpful assistance.
Various chapters are based on scientific papers that have been published
atinternationalconferencesandinscientificjournals.Wewouldliketothank
theco-authorsofthesepapers,especiallyourcollaboratorsAndreasGlowatz,
FriedrichHapkeandJu¨rgenSchlo¨ffelfortheircontributionsandsteadysup-
port. We would also like to acknowledge the work of Junhao Shi, who was
oneofthedrivingforces,whenthisprojectstartedandhewasaPhDstudent
in the group. We would also like to thank Arne Sticht, Ren´e Krenz-B˚a˚ath
and Tim Warode for helpful discussions.
Our special thanks go to Michael Miller who spent a huge effort in care-
fully proof-reading and improving the final manuscript. Finally, we would
like to thank Lisa Jungmann for helping with the layout of figures and for
creating the cover design.
vii
Contents
Preface v
Acknowledgments vii
1 Introduction 1
2 Preliminaries 9
2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Stuck-at Faults . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Delay Faults . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Simple ATPG Framework . . . . . . . . . . . . . . . . . . . . 16
2.4 Classical ATPG Algorithms . . . . . . . . . . . . . . . . . . . 20
2.4.1 Stuck-at Faults . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Delay Faults . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Benchmarking . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3 Boolean Satisfiability 29
3.1 SAT Solver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Advances in SAT . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.1 Boolean Constraint Propagation . . . . . . . . . . . . 31
3.2.2 Conflict Analysis . . . . . . . . . . . . . . . . . . . . . 32
3.2.3 Variable Selection Strategies . . . . . . . . . . . . . . 35
3.2.4 Correctness and Unsatisfiable Cores . . . . . . . . . . 35
3.2.5 Optimization Techniques . . . . . . . . . . . . . . . . 36
3.3 Circuit-to-CNF Conversion . . . . . . . . . . . . . . . . . . . 38
3.4 Circuit-Oriented SAT . . . . . . . . . . . . . . . . . . . . . . 41
ix
x CONTENTS
4 SAT-Based ATPG 43
4.1 Basic Problem Transformation . . . . . . . . . . . . . . . . . 44
4.2 Structural Information . . . . . . . . . . . . . . . . . . . . . . 46
4.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 49
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Learning Techniques 53
5.1 Introductory Example . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Concepts for Reusing Learned Information . . . . . . . . . . . 55
5.2.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.2 Tracking Conflict Clauses . . . . . . . . . . . . . . . . 57
5.3 Heuristics for ATPG . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.1 Notation. . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.2 Incremental SAT-Based ATPG . . . . . . . . . . . . . 60
5.3.3 Enhanced Circuit-Based Learning . . . . . . . . . . . 63
5.4 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 66
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6 Multiple-Valued Logic 71
6.1 Four-Valued Logic . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.1 Industrial Circuits . . . . . . . . . . . . . . . . . . . . 72
6.1.2 Boolean Encoding . . . . . . . . . . . . . . . . . . . . 73
6.1.3 Encoding Efficiency . . . . . . . . . . . . . . . . . . . 75
6.1.4 Concrete Encoding . . . . . . . . . . . . . . . . . . . . 77
6.2 Multi-input Gates . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.1 Modeling of Multi-input Gates . . . . . . . . . . . . . 79
6.2.2 Bounded Multi-input Gates . . . . . . . . . . . . . . . 82
6.2.3 Clause Generation . . . . . . . . . . . . . . . . . . . . 83
6.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 84
6.3.1 Four-Valued Logic . . . . . . . . . . . . . . . . . . . . 84
6.3.2 Multi-input Gates . . . . . . . . . . . . . . . . . . . . 85
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7 Improved Circuit-to-CNF Conversion 89
7.1 Hybrid Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.2 Incremental Instance Generation . . . . . . . . . . . . . . . . 94
7.2.1 Run Time Analysis . . . . . . . . . . . . . . . . . . . . 94
7.2.2 Incremental Approach . . . . . . . . . . . . . . . . . . 99
7.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 104
7.3.1 Hybrid Logic . . . . . . . . . . . . . . . . . . . . . . . 105
CONTENTS xi
7.3.2 Incremental Instance Generation . . . . . . . . . . . . 107
7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8 Branching Strategies 113
8.1 Standard Heuristics of SAT Solvers . . . . . . . . . . . . . . . 113
8.2 Decision Strategies . . . . . . . . . . . . . . . . . . . . . . . . 114
8.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 115
8.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9 Integration into Industrial Flow 119
9.1 Industrial Environment . . . . . . . . . . . . . . . . . . . . . 120
9.2 Integration of SAT-Based ATPG . . . . . . . . . . . . . . . . 123
9.3 Test Pattern Compactness . . . . . . . . . . . . . . . . . . . . 125
9.3.1 Observability at Outputs . . . . . . . . . . . . . . . . 125
9.3.2 Applying Local Don’t Cares . . . . . . . . . . . . . . . 127
9.4 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 129
9.4.1 Integration . . . . . . . . . . . . . . . . . . . . . . . . 129
9.4.2 Test Pattern Compactness . . . . . . . . . . . . . . . . 132
9.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10 Delay Faults 137
10.1 Transition Delay . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.2 Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2.1 Non-robust Tests . . . . . . . . . . . . . . . . . . . . . 141
10.2.2 Robust Test Generation . . . . . . . . . . . . . . . . . 143
10.2.3 Industrial Application . . . . . . . . . . . . . . . . . . 145
10.2.4 Structural Classification . . . . . . . . . . . . . . . . . 149
10.3 Encoding Efficiency for Path Delay Faults . . . . . . . . . . . 151
10.3.1 Compactness of Boolean Representation . . . . . . . . 153
10.3.2 Efficiency of Compact Encodings . . . . . . . . . . . . 155
10.3.3 Encoding Selection . . . . . . . . . . . . . . . . . . . . 157
10.4 Incremental Approach . . . . . . . . . . . . . . . . . . . . . . 158
10.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . 161
10.5.1 Transition Delay Faults . . . . . . . . . . . . . . . . . 161
10.5.2 Encoding Efficiency for Path Delay Faults . . . . . . . 163
10.5.3 Robust and Non-robust Tests . . . . . . . . . . . . . . 166
10.5.4 Incremental Approach . . . . . . . . . . . . . . . . . . 168
10.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
xii CONTENTS
11 Summary and Outlook 173
Bibliography 177
Index 189