Technology evolution for silicon nano-electronics : selected, peer reviewed papers from the proceedings of the International Symposium on Technology Evolution for Silicon Nano-Electronics 2010, June 3-5, 2010, Tokyo Institute of Technology, Tokyo, Japan

245 Pages·2011·29.014 MB·English

by  Seiichi Miyazaki, Hitoshi Tabata

Technology Evolution
for
Silicon
Nano-Electronics
Edited by
Seiichi Miyazaki
Hitoshi Tabata
Technology Evolution
for Silicon
Nano-Electronics
Selected, peer reviewed papers from the proceedings of
the International Symposium on
Technology Evolution for Silicon Nano-Electronics 2010,
June 3-5, 2010,
Tokyo Institute of Technology, Tokyo, Japan
Edited by
Seiichi Miyazaki and Hitoshi Tabata
Copyright  2011 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be
reproduced or transmitted in any form or by any means without the
written permission of the publisher.

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Volume 470 of
Key Engineering Materials
ISSN 1013-9826
Full text available online at http://www.scientific.net

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PREFACE

Silicon ultra-large scale integrated circuits (ULSIs) are now being faced to various
physical limits for further scaling. Therefore, it is strongly required to establish the basic
science and technology in realizing nano-scale complementary metal-oxide-semiconductor
devices (Nano-CMOS) with high performance, new functionality and large-scale integration.
For this purpose, Scientific Research on Priority Areas (No.18063012, “Post-scaling”),
supported by the Ministry of Education, Culture, Sports, Science and Technology in Japan,
have been conducted for 4 years starting in 2006.
“International Symposium on Technology Evolution for Silicon Nano-Electronics
(ISTESNE)” has been organized to offer an opportunity for discussions and exchange of
recent progress through this research project and latest achievements of related regions. It is
absolutely necessary to promote collaboration among the research communities for clearing
the complex issues in the interdisciplinary research fields. ISTESNE was held in Tokyo
Institute of Technology, Tokyo, Japan on June 3-5, 2010. At the symposium, 2 keynote
speeches, 8 invited papers, 28 oral papers, and 48 poster papers were presented. We would
like to sincerely thank all authors and participants for their high quality contribution to
scientific and technological progress for future Si nanoelectronics.
The ISTESNE committee would like to thank the chairpersons for their capable handling
of the sessions and the referees for their assistance in producing this volume. Finally, we
would like to appreciate the Japan Society of Applied Physics, the Institute of Electronics,
Information and Communication Engineers, and all companies and organizations for financial
supports to Scientific Research on Priority Areas by the Ministry of Education, Culture,
Sports, Science and Technology in Japan.

Organizing Committee Chair, Shigeaki Zaima (Nagoya Univ.)
Program Committee Chair, Seiichi Miyazaki (Nagoya Univ.)
Steering Committee Chair, Masaru Hori (Nagoya Univ.)
Sponsored by

Scientific Research on Priority Areas (No.18063012, “Post-scaling”), by the Ministry of
Education, Culture, Sports, Science and Technology

Supported by

The Japan Society of Applied Physics, Division of Silicon Technology
The Japan Society of Applied Physics, Division of Plasma Electronics
The Japan Society of Applied Physics, Division of Thin Film and Surface Physics
The Institute of Electronics, Information and Communication Engineers, Electronics Society
Symposium Organization

Organizing Committee
Chair: Shigeaki Zaima (Nagoya Univ.)
Vice-Chair: Kazuya Masu (Tokyo Institute of Technology)
Shinichi Takagi (The Univ. of Tokyo) Yasuhiro Horiike (National Institute for Materials
Masaru Hori (Nagoya Univ.) Science)
Hitoshi Tabata (The Univ. of Tokyo) Yukio Yasuda (Tohoku Univ.)
Seiichi Miyazaki (Nagoya Univ.) Akira Toriumi (The Univ. of Tokyo)
Toshiro Hiramoto (The Univ. of Tokyo) Masao Fukuma (Renesas Electronics Corporation)
Hisatsune Watanabe (Semiconductor Leading Edge Tadashi Shibata (The Univ. of Tokyo)
Technologies, Inc.)

Program Committee
Chair: Seiichi Miyazaki (Nagoya Univ.)
Vice-Chair: Toshiro Hiramoto (The Univ. of Tokyo) and Shinichi Takagi (The Univ. of Tokyo)
Akira Sakai (Osaka Univ.) Nobuya Mori (Osaka Univ.)
Taizoh Sadoh (Kyushu Univ.) Tetsu Tanaka (Tohoku Univ.)
Hiroya Ikeda (Shizuoka Univ.) Heiji Watanabe (Osaka Univ.)
Takashi Nakayama (Chiba Univ.) Masao Sakuraba (Tohoku Univ.)
Yukiharu Uraoka (Nara Inst. of Sci. and Tech.) Osamu Nakatsuka (Nagoya Univ.)
Yoshinari Kamakura (Osaka Univ.) Wakana Takeuchi (Nagoya Univ.)
Nobuyuki Sano (Univ. of Tsukuba)

Steering Committee
Chair: Masaru Hori (Nagoya Univ.)
Vice-Chair: Hitoshi Tabata (The Univ. of Tokyo) and Kenji Shiraishi (Univ. of Tsukuba)
Kazuo Tsutsui (Tokyo Inst. of Tech.) Mitsuo Sakashita (Nagoya Univ.)
Koji Kita (The Univ. of Tokyo) Hiroki Kondo (Nagoya Univ.)
Kuniyuki Kakushima (Tokyo Inst. of Tech.) Keigo Takeda (Nagoya Univ.)
Noboru Ishihara (Tokyo Inst. of Tech.)
Table of Contents
Preface, Sponsors and Committees
I. Nano-Structure Physics and Nano-Material Science
High Mobility Ge-Based CMOS Device Technologies
S. Takagi, S. Dissanayake and M. Takenaka 1
SiGe-Mixing-Triggered Rapid-Melting-Growth of High-Mobility Ge-On-Insulator
T. Sadoh, K. Toko, M. Kurosawa, T. Tanaka, T. Sakane, Y. Ohta, N. Kawabata, H. Yokoyama
and M. Miyao 8
Impact of Self-Heating Effect on the Electrical Characteristics of Nanoscale Devices
Y. Kamakura, T. Zushi, T. Watanabe, N. Mori and K. Taniguchi 14
Functional Device Applications of Nanosilicon
N. Koshida, T. Ohta, Y. Hirano, R. Mentek and B. Gelloz 20
Tunable Single-Electron Turnstile Using Discrete Dopants in Nanoscale SOI-FETs
D. Moraru, K. Yokoi, R. Nakamura, S. Miki, T. Mizuno and M. Tabe 27
KFM Observation of Electron Charging and Discharging in Phosphorus-Doped SOI
Channel
M. Anwar, D. Moraru, Y. Kawai, M. Ligowski, T. Mizuno, R. Jabłoński and M. Tabe 33
Photoluminescence Characteristics of Ultra-Thin Silicon-on-Insulator at Low Temperatures
Y. Sakurai, S. Nomura, K. Shiraishi, K. Ohmori and K. Yamada 39
Investigation about I-V Characteristics in a New Electronic Structure Model of the Ohmic
Contact for Future Nano-Scale Ohmic Contact
Y. Takada, M. Muraguchi, T. Endoh, S. Nomura and K. Shiraishi 43
Collective Electron Tunneling Model in Si-Nano Dot Floating Gate MOS Structure
M. Muraguchi, Y. Sakurai, Y. Takada, Y. Shigeta, M. Ikeda, K. Makihara, S. Miyazaki, S.
Nomura, K. Shiraishi and T. Endoh 48
Electronic Structure and Spin-Injection of Co-Based Heusler Alloy/ Semiconductor
Junctions
H. Itoh, S. Honda and J. Inoue 54
First-Principles Calculations of the Dielectric Constant for the GeO Films
2
M. Tamura, J. Nakamura and A. Natori 60
Nanosize Electronics Material Analysis by Local Quantities Based on the Rigged QED
Theory
M. Senami, Y. Ikeda, T. Hara and A. Tachibana 66
Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic
CMOS Transistors
T. Mizuno, M. Hasegawa and T. Sameshima 72
Effect of Al O Deposition and Subsequent Annealing on Passivation of Defects in Ge-Rich
2 3
SiGe-on-Insulator
H.G. Yang, M. Iyota, S. Ikeura, D. Wang and H. Nakashima 79
II. Nano-Processing and Nano-Devices
Controlled Synthesis of Carbon Nanowalls for Carbon Channel Engineering
H. Kondo, M. Hori, W. Takeuchi and M. Hiramatsu 85
Resistive Memory Utilizing Ferritin Protein with Nano Particle
M. Uenuma, K. Kawano, B. Zheng, M. Horita, S. Yoshii, I. Yamashita and Y. Uraoka 92
Atomically Controlled Plasma Processing for Group IV Quantum Heterostructure
Formation
M. Sakuraba, K. Sugawara and J. Murota 98
Nanometer-Scale Characterization Technique for Si Nanoelectric Materials Using
Synchrotron Radiation Microdiffraction
S. Kimura, Y. Imai, O. Sakata and A. Sakai 104
Generation and Growth of Atomic-Scale Roughness at Surface and Interface of Silicon
Dioxide Thermally Grown on Atomically Flat Si Surface
Y. Hayashi, R. Hasunuma and K. Yamabe 110
b Technology Evolution for Silicon Nano-Electronics
Nano-Surface Modification of Silicon with Ultra-Short Pulse Laser Process
Y. Setsuhara and M. Hashida 117
Evaluation of Strained Silicon by Electron Back Scattering Pattern Compared with Raman
Measurement and Edge Force Model Calculation
M. Tomita, D. Kosemura, M. Takei, K. Nagata, H. Akamatsu and A. Ogura 123
Development of New Methods for Fine-Wiring in Si Using a Wet Catalytic Reaction
C.L. Lee, T. Sugita, K. Tatsumi, S. Ikeda and M. Matsumura 129
III. Nano-System Functionality Integration
Optical Response of Si-Quantum-Dots/NiSi-Nanodots Stack Hybrid Floating Gate in MOS
Structures
N. Morisawa, M. Ikeda, K. Makihara and S. Miyazaki 135
Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory
Application
Y.L. Pei, T. Hiraki, T. Kojima, T. Fukushima, M. Koyanagi and T. Tanaka 140
Strained Ge and Ge Sn Technology for Future CMOS Devices
1-x x
O. Nakatsuka, S. Takeuchi, Y. Shimura, A. Sakai and S. Zaima 146
Improved Electrical Properties and Thermal Stability of GeON Gate Dielectrics Formed by
Plasma Nitridation of Ultrathin Oxides on Ge(100)
H. Watanabe, K. Kutsuki, I. Hideshima, G. Okamoto, T. Hosoi and T. Shimura 152
Structural Change during the Formation of Directly Bonded Silicon Substrates
T. Kato, T. Ueda, Y. Ohara, J. Kikkawa, Y. Nakamura, A. Sakai, O. Nakatsuka, S. Zaima, E.
Toyoda, K. Izunome, Y. Imai, S. Kimura and O. Sakata 158
Microscopic Structure of Directly Bonded Silicon Substrates
T. Kato, Y. Ohara, T. Ueda, J. Kikkawa, Y. Nakamura, A. Sakai, O. Nakatsuka, M. Ogawa, S.
Zaima, E. Toyoda, H. Isogai, T. Senda, K. Izunome, H. Tajiri, O. Sakata and S. Kimura 164
Formation of Nanotubes of Carbon by Joule Heating of Carbon-Contaminated Si
Nanochains
H. Kohno and T. Nogami 171
Si Nanodot Device Fabricated by Thermal Oxidation and their Applications
Y. Takahashi, M.Y. Jo, T. Kaizawa, Y. Kato, M. Arita, A. Fujiwara, Y. Ono, H. Inokawa and J.B.
Choi 175
Influences of Carrier Transport on Drain-Current Variability of MOSFETs
K. Ohmori, K. Shiraishi and K. Yamada 184
Resistive Switching in NiO Bilayer Films with Different Crystallinity Layers
K. Kita, A. Eika, T. Nishimura, K. Nagashio and A. Toriumi 188
IV. Nano-Device Integrity for Variability / Fluctuation Management
and Integration
Analysis of Threshold Voltage Variations in Fin Field Effect Transistors
K. Tsutsui, Y. Kobayashi, K. Kakushima, P. Ahmet, V.R. Rao and H. Iwai 194
Capture/Emission Processes of Carriers in Heterointerface Traps Observed in the Transient
Charge-Pumping Characteristics of SiGe/Si-Hetero-Channel pMOSFETs
T. Tsuchiya, K. Yoshida, M. Sakuraba and J. Murota 201
Quasi-Ballistic Transport in Nano-Scale Devices: Boundary Layer, Potential Fluctuation,
and Coulomb Interaction
N. Sano and T. Karasawa 207
Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs
T. Hiramoto, T. Saraya and C.H. Lee 214
Discrete Dopant Effects on Threshold Voltage Variation in Double-Gate and Gate-All-
Around Metal-Oxide-Semiconductor Field-Effect-Transistors
N. Mori, Y. Kamakura, G. Mil'nikov and H. Minari 218
Interconnect Design Challenges in Nano CMOS Circuit
K. Masu, S. Amakawa, H. Ito and N. Ishihara 224
Key Engineering Materials Vol. 470 (2011) pp 1-7
© (2011) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/KEM.470.1
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