TDA2Px ADAS Applications Processor 23mm Package (ABZ Package)

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TDA2P-ABZ
SPRS990F–DECEMBER2016–REVISEDDECEMBER2018
TDA2Px ADAS Applications Processor
23mm Package (ABZ Package)
Silicon Revision 1.0
1 Device Overview
1.1 Features
1
• ArchitectureDesignedforADASApplications Controller
• Video,Image,andGraphicsProcessingSupport • 2-PortGigabit Ethernet(GMAC)
– Full-HDVideo(1920× 1080p,60fps) • UptoTwoControllerAreaNetwork(DCAN)
Modules
– MultipleVideoInputandVideoOutput
• DualArm®Cortex®-A15Microprocessor – CAN2.0BProtocol
Subsystem • ModularControllerAreaNetwork(MCAN)Module
• UptoTwoC66xFloating-PointVLIWDSP – CAN2.0BProtocolwithAvailableFD(Flexible
DataRate)Functionality
– FullyObject-CodeCompatiblewithC67xand
C64x+ • PCIExpress®3.0PortwithIntegratedPHY
– UptoThirty-Two16 ×16-BitFixed-Point – One2-LaneGen2-Compliant Port
MultipliesperCycle – orTwo1-LaneGen2-Compliant Ports
• Upto2.5MBofOn-ChipL3RAM • Sixteen32-Bit General-PurposeTimers
• Level3(L3)andLevel4(L4)Interconnects • 32-Bit MPUWatchdogTimer
• TwoDDR2/DDR3/DDR3LMemoryInterface • TenConfigurableUART/IrDA/CIRModules
(EMIF) Modules • FourMultichannelSerialPeripheralInterfaces
– SupportsuptoDDR2-800andDDR3-1333 (McSPI)
– Upto2GBSupportedperEMIF • QuadSPIInterface
• DualArm® Cortex®-M4ImageProcessingUnits • FiveInter-IntegratedCircuit(I2C)Ports
(IPU) • SATAInterface
• VisionAccelerationPac • EightMultichannelAudioSerialPort(McASP)
– UptoTwoEmbeddedVisionEngines(EVEs) Modules
• ImagingSubsystem(ISS) • SuperSpeedUSB3.0Dual-RoleDevice
– ImageSignalProcessor(ISP) • ThreeHigh-SpeedUSB2.0Dual-RoleDevices
– WideDynamicRangeandLensDistortion • FourMultiMediaCard/SecureDigital/Secure Digital
Correction(WDRandMeshLDC) Input OutputInterfaces( MMC™/SD®/SDIO)
– OneCameraAdaptationLayer(CAL_B) • Upto247General-PurposeI/O(GPIO)Pins
• IVA-HDSubsystem • Real-TimeClockSubsystem(RTCSS)
• DisplaySubsystem • DeviceSecurityFeatures
– DisplayControllerwithDMAEngineandupto – HardwareCryptoAcceleratorsandDMA
ThreePipelines – Firewalls
– HDMI™Encoder:HDMI1.4aandDVI1.0 – JTAG® Lock
Compliant
– SecureKeys
• 2D-GraphicsAccelerator(BB2D)Subsystem
– SecureROMandBoot
– Vivante® GC320Core
– CustomerProgrammableKeysandOTP Data
• VideoProcessingEngine(VPE)
• Power, Reset,andClockManagement
• Dual-CorePowerVR®SGX5443DGPU
• On-ChipDebugWithCToolsTechnology
• TwoVideoInputPort(VIP)Modules
• AutomotiveAEC-Q100Qualified
– SupportforuptoEightMultiplexedInputPorts
• 28-nmCMOSTechnology
• General-PurposeMemoryController(GPMC)
• 23mm× 23mm,0.8-mmPitch, 760-PinBGA
• EnhancedDirectMemoryAccess(EDMA) (ABZ)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TDA2P-ABZ
SPRS990F–DECEMBER2016–REVISEDDECEMBER2018 www.ti.com
1.2 Applications
• Mono,StereoorTri-OpticFrontCamera • LVDSorEthernetSurroundView
– ObjectDetection – 2Dsurroundview
– PedestrianDetection – 3Dsurroundview
– TrafficSignRecognition – Rearobject detection
– LaneDetectionandDepartureWarning – Parkingassist
– AutomaticEmergencyBraking – PedestrianDetection
– AdaptiveCruiseControl – Lanetracking
– ForwardCollisionWarning – DriveRecording
– HighBeamAssist • SensorFusion– Vision,Radar,Ultrasonic,Lidar
sensors
– Objectdatafusion
– Rawdatafusion
1.3 Description
TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to
meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family
enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power
and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving
experience.
The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of
ADAS applications including front camera, park assist, surround view and sensor fusion on a single
architecture.
The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed
and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac,
Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for
decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for
rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of
peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view
systems, displays,CANandGigBEthernetAVB.
The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs)
offloading the vision analytics functionality from the application processor while also reducing the power
footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for
efficient programexecutionandavectorcoprocessorfor specializedvisionprocessing.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,
including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a
debugginginterfaceforvisibilityintosourcecodeexecution.
Cryptographic acceleration is available in all devices. All other supported security features, including
support for secure boot, debug security and support for trusted execution environment are available on
High-Security(HS)devices.FormoreinformationaboutHSdevices, contactyourTIrepresentative.
TheTDA2PxADASprocessorisqualifiedaccordingtotheAEC-Q100standard.
DeviceInformation
PARTNUMBER PACKAGE BODYSIZE
TDA2Px FCBGA(760) 23.0mm×23.0mm
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1.4 Functional Block Diagram
Figure1-1isfunctionalblockdiagramof thesuperset.
TDA2Px Superset
MPU DSP IVAHD BB2D
(2xArm (2x C66x 1080p Video (GC320 2D)
Cortex–A15) Coprocessors) Coprocessor
GPU VisionAccelerationPac Display Subsystem
(Dual-Core
2x EVEAnalytic Processors Secure Boot
SGX544 3D) Overlay
Debug
1x GFX Pipeline
Security
IPU 1 ISS 3x Video Pipelines
TEE
(DualCortex–M4) ISP CAL_B
(HS devices)
IPU 2
WDR & Mesh LDC HDMI 1.4a LCD1/2/3
(DualCortex–M4)
VPE 22xx MMMMUU VIP1 VIP2 JTAG PLLs OSC
High-Speed Interconnect
System Connectivity
Spinlock Timers x16 EDMA 1x USB 3.0 PCIe SS x2
Dual-Role FS/HS/SS
Mailbox x13 WDT SDMA
w/ PHYs GMACAVB
GPIO x8 PWM SS x3
3x USB 2.0
RTC SS Dual-Role FS/HS
1x w/ PHY
2x w/ ULPI
Serial Interfaces
Program/Data Storage
UART x10 QSPI
MMC / SD x4 SATA
McSPI x4 McASPx8 GPMC / ELM EMIF x2
Up to 2.5MB
(NAND/NOR/ 2x 32b
DCAN x2 MCAN-FD x1 RAM w/ ECC Async) DDR2/3(L) w/ ECC(1)
I2C x5
OCMC 256KB ROM DMM
intro-001
Copyright © 2016,Texas Instruments Incorporated
Figure1-1.TDA2PxBlockDiagram
(1) ECCisonlyavailableonEMIF1.
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Table of Contents
1 DeviceOverview......................................... 1 6.5 ISS................................................. 340
.............................................. .................................................
1.1 Features 1 6.6 IVA 340
........................................... ................................................
1.2 Applications 2 6.7 EVE 341
............................................ .................................................
1.3 Description 2 6.8 IPU 342
........................... ................................................
1.4 FunctionalBlockDiagram 3 6.9 VPE 343
2 Revision History......................................... 5 6.10 GPU................................................ 345
3 DeviceComparison ..................................... 6 6.11 MemorySubsystem................................ 346
............................ ....................
3.1 DeviceComparisonTable 6 6.12 InterprocessorCommunication 349
..................................... .................................
3.2 RelatedProducts 8 6.13 Interrupt Controller 350
4 TerminalConfigurationandFunctions.............. 9 6.14 EDMA.............................................. 351
.......................................... .........................................
4.1 PinDiagram 9 6.15 Peripherals 352
......................................... ....................................
4.2 PinAttributes 9 6.16 On-Chip Debug 367
4.3 SignalDescriptions.................................. 77 7 Applications,Implementation,andLayout...... 370
.................................... ........................................
4.4 PinMultiplexing 118 7.1 Introduction 370
...................... ...............................
4.5 ConnectionsforUnusedPins 134 7.2 PowerOptimizations 371
5 Specifications ......................................... 135 7.3 CorePowerDomains.............................. 385
5.1 AbsoluteMaximumRatings(1)..................... 136 7.4 Single-EndedInterfaces........................... 397
....................................... ..............................
5.2 ESDRatings 137 7.5 DifferentialInterfaces 399
.................... ..........................
5.3 Power-OnHours(POH)Limits 137 7.6 ClockRoutingGuidelines 420
5.4 RecommendedOperatingConditions(5)........... 137 7.7 DDR2/DDR3BoardDesignandLayout
..........................................
..................... Guidelines 422
5.5 OperatingPerformancePoints 141
.................... 8 DeviceandDocumentationSupport.............. 457
5.6 PowerConsumptionSummary 162
.
........................... 8.1 DeviceNomenclatureandOrderableInformation 457
5.7 ElectricalCharacteristics 162
................................
5.8 VPPSpecificationsforOne-TimeProgrammable 8.2 ToolsandSoftware 459
...................................... ............................
(OTP)eFuses 169 8.3 DocumentationSupport 460
............... .
5.9 ThermalResistanceCharacteristics 170 8.4 ReceivingNotificationofDocumentationUpdates 460
5.10 TimingRequirementsandSwitching 8.5 CommunityResources............................. 461
.....................................
Characteristics 172 ........................................
8.6 Trademarks 461
6 DetailedDescription.................................. 331 ...................
8.7 ElectrostaticDischargeCaution 461
.........................................
6.1 Description 331 ..............................
8.8 ExportControlNotice 461
.........................
6.2 FunctionalBlockDiagram 331 ............................................
8.9 Glossary 461
................................................
6.3 MPU 333 9 MechanicalPackagingInformation............... 462
...................................
6.4 DSPSubsystem 336 ...................................
9.1 MechanicalData 462
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2 Revision History
ChangesfromMarch17,2018toDecember15,2018(fromERevision(March2018)toFRevision) Page
• AddedTDA2PHFdeviceandspeedgradeUtoTable3-1,DeviceComparison............................................ 6
• AddedclarificationnotesregardingX5777xpartnumbertoTable3-1,DeviceComparison............................... 6
• AddedTDA2PHFxdeviceinPinAttributessection ............................................................................. 9
• RemovedwrongplacedballsinTable4-19,GPIOsSignalDescriptions.................................................. 102
• Updatedporz,resetnandrstoutnsignaldescriptionsinTable4-22PRCMSignalDescriptions....................... 110
• AddedtablenoteformaximumvalidinputvoltageonanIOpintoSection5.1,AbsoluteMaximumRatingOver
JunctionTemperatureRange.................................................................................................... 136
• AddedclarificationnoteregardingTSHUTfeature. .......................................................................... 141
• AddedTDA2PxxUspeedgradetoTable5-1,SpeedGradeMaximumFrequency. ..................................... 141
• AddeddefinitionforMPUOPP_LOWinVoltageDomainsOperatingPerformancePointsandSupportedOPPvs
MaxFrequencytables ............................................................................................................ 142
• UpdatedSYS_32KtoFUNC_32K_CLKinTable5-5,MaximumSupportedFrequency................................. 144
• AddedIvppspecificationinTable5-14,RecommendedOperatingConditionsforOTPeFuseProgramming ....... 169
• UpdatedSection5.8.3,ImpacttoYourHardwareWarranty................................................................. 170
• UpdatedPowerSupplySequencessection.................................................................................... 174
• UpdatedsystemclocknamesinSection5.10.4,ClockSpecifications..................................................... 183
• UpdatedmanualmodeandtimingtablesforDSS,GMAC-RGMII,andMMC2........................................... 221
• AddedmissingballsinTable5-70,McSPI3/4IOSETs ...................................................................... 261
• UpdatedphasepolarityinallQSPItimingfigures............................................................................. 264
• RemovedreferencestoOpenGLinSection6.10,GPU...................................................................... 345
• UpdatedSection7.3.5,PowerSupplyMapping............................................................................... 389
• AddednewSection7.3.7,LossofInputPowerEvent........................................................................ 390
• Addedspeedgrade"U"toTable8-1,NomenclatureDescription .......................................................... 458
• AddedclarificationnotesregardingX5777xpartnumberin,NomenclatureDescription................................ 458
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3 Device Comparison
3.1 Device Comparison Table
Table3-1showsacomparisonbetweendevices, highlightingthedifferences.
Table3-1. DeviceComparison(6)
Features Device
TDA2PSxx TDA2PHxx
TDA2PSXx TDA2PHGx TDA2PHFx TDA2PHVx TDA2PHAx
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24]BasePN 51(0x33) 42(0x2A) 41(0x29) 38(0x26) 37(0x25)
registerbitfieldvalue(5)(6)
Processors/Accelerators
SpeedGrades T R,D U R,D R,D
ArmDualCortex-A15 MPUcore0 Yes Yes Yes Yes Yes
MicroprocessorSubsystem
MPUcore1 Yes No Yes No No
C66xVLIWDSP DSP1 Yes Yes Yes Yes Yes
(withL1DECC)
DSP2 Yes Yes Yes Yes Yes
(withL1DECC)
BitBLT2DHardware BB2D Yes Yes No No No
AccelerationEngine
DisplaySubsystem VOUT1 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
VOUT2 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
VOUT3 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
HDMI Yes Yes Yes Yes Yes
EmbeddedVisionEngine EVE1 Yes Yes Yes Yes Yes
EVE2 Yes Yes Yes Yes Yes
ArmDualCortex-M4Image IPU1 Yes Yes Yes Yes Yes
ProcessingUnit
IPU2 Yes Yes Yes Yes Yes
ImageVideoAccelarator IVA Yes Yes Yes Yes No
SGX544Dual-Core3D GPU Yes Yes No No No
GraphicsProcessingUnit
ImagingSubsystemwithWDR ISP Yes Yes Yes Yes No
&LDC(ISS) WDR&MeshLDC(4) Yes Yes Yes Yes No
CAL_B Yes Yes Yes Yes No
VideoInput VIP1 vin1a Yes Yes Yes Yes Yes
Port
vin1b Yes Yes Yes Yes Yes
vin2a Yes Yes Yes Yes Yes
vin2b Yes Yes Yes Yes Yes
VIP2 vin3a Yes Yes Yes Yes Yes
vin3b Yes Yes Yes Yes Yes
vin4a Yes Yes Yes Yes Yes
vin4b Yes Yes Yes Yes Yes
VIP3 vin5a No No No No No
vin6a No No No No No
VideoProcessingEngine VPE Yes Yes Yes Yes Yes
CameraAdaptationLayer CSI2_0 No No No No No
(CAL)CameraSerialInterface (CLK+4Data)
2(CSI2)
CSI2_1 No No No No No
(CLK+2Data)
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Table3-1.DeviceComparison(6) (continued)
Features Device
TDA2PSxx TDA2PHxx
TDA2PSXx TDA2PHGx TDA2PHFx TDA2PHVx TDA2PHAx
Program/DataStorage
On-ChipSharedMemory OCMC_RAM1 512KB 512KB 512KB 512KB 512KB
(RAM)
OCMC_RAM2 1MB 1MB 1MB 1MB 1MB
OCMC_RAM3 1MB 1MB 1MB 1MB 1MB
General-PurposeMemory GPMC Yes Yes Yes Yes Yes
Controller
DDR2/DDR3/DDR3LMemory EMIF1(withR-mod- upto2GB upto2GB upto2GB upto2GB upto2GB
Controller(2) WECC)
EMIF2 upto2GB upto2GB upto2GB upto2GB upto2GB
DynamicMemoryManager DMM Yes Yes Yes Yes Yes
RadioSupport
AudioTrackingLogic ATL No No No No No
ViterbiCoprocessor VCP1 No No No No No
VCP2 No No No No No
Peripherals
ControllerAreaNetwork DCAN1(3) Yes Yes Yes Yes Yes
Interface(CAN) DCAN2(3) Yes Yes Yes Yes Yes
MCANwithFD(3) Yes Yes Yes Yes Yes
EnhancedDMA EDMA Yes Yes Yes Yes Yes
SystemDMA SDMA Yes Yes Yes Yes Yes
EthernetSubsystem(Ethernet GMAC_SW[0] Yes Yes Yes Yes Yes
SS)
GMAC_SW[1] Yes Yes Yes Yes Yes
General-PurposeIO GPIO upto247 upto247 upto247 upto247 upto247
Inter-IntegratedCircuitInterface I2C 5 5 5 5 5
SystemMailboxModule MAILBOX 13 13 13 13 13
MediaLocalBus MLB No No No No No
Multi-ChannelAudioSerialPort McASP1 16serializers 16serializers 16serializers 16serializers 16serializers
McASP2 16serializers 16serializers 16serializers 16serializers 16serializers
McASP3 4serializers 4serializers 4serializers 4serializers 4serializers
McASP4 4serializers 4serializers 4serializers 4serializers 4serializers
McASP5 4serializers 4serializers 4serializers 4serializers 4serializers
McASP6 4serializers 4serializers 4serializers 4serializers 4serializers
McASP7 4serializers 4serializers 4serializers 4serializers 4serializers
McASP8 4serializers 4serializers 4serializers 4serializers 4serializers
MultiMediaCard/Secure MMC1 Yes Yes Yes Yes Yes
Digital/SecureDigitalInput
MMC2 Yes Yes Yes Yes Yes
OutputInterface
(MMC/SD/SDIO) MMC3 Yes Yes Yes Yes Yes
MMC4 Yes Yes Yes Yes Yes
PCIExpress3.0Portwith PCIe_SS1 Yes Yes Yes Yes Yes
IntegratedPHY
PCIe_SS2 Yes Yes Yes Yes Yes
SATAGen2Interface SATA Yes Yes Yes Yes Yes
Real-TimeClockSubsystem RTCSS Yes Yes Yes Yes Yes
ProgrammableReal-TimeUnit PRU-ICSS No No No No No
SubsystemandIndustrial
CommunicationSubsystem
MultichannelSerialPeripheral McSPI 4 4 4 4 4
Interface
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Table3-1.DeviceComparison(6) (continued)
Features Device
TDA2PSxx TDA2PHxx
TDA2PSXx TDA2PHGx TDA2PHFx TDA2PHVx TDA2PHAx
HDQ1W HDQ1W No No No No No
QuadSPI QSPI Yes Yes Yes Yes Yes
SpinlockModule SPINLOCK Yes Yes Yes Yes Yes
KeyboardController KBD No No No No No
Timers,General-Purpose TIMER 16 16 16 16 16
Timer,Watchdog WATCHDOGTIMER Yes Yes Yes Yes Yes
Pulse-WidthModulation PWMSS1 Yes Yes Yes Yes Yes
Subsystem
PWMSS2 Yes Yes Yes Yes Yes
PWMSS3 Yes Yes Yes Yes Yes
UniversalAsynchronous UART 10 10 10 10 10
Receiver/Transmitter
UniversalSerialBus(USB3.0) USB1(SuperSpeed, Yes Yes Yes Yes Yes
Dual-Role-Device
[DRD])
UniversalSerialBus(USB2.0) USB2(HighSpeed, Yes Yes Yes Yes Yes
Dual-Role-Device
[DRD],with
embeddedHSPHY)
USB3(HighSpeed, Yes Yes Yes Yes Yes
OTG2.0,withULPI)
USB4(HighSpeed, Yes Yes Yes Yes Yes
OTG2.0,withULPI)
(1) DSSclockjittercanbeimprovedbyprovidinganexternalclocksource(viainputsvin1a_clk,vin1b_clk,wakeup0,wakeup1)orfrom
internalSATAorPCIePLLs.
(2) IntheUnifiedL3memorymap,thereismaximumof2GBofSDRAMspacewhichisavailabletoallL3initiatorsincludingMPU(MPU,
GPU,DSP,IVA,DMA,etc).TypicallythisspaceisinterleavedacrossbothEMIFstooptimizememoryperformance.Ifasystem
populates>2GBofphysicalmemory,thatadditionaladdressablespacecanbeaccessedonlybytheMPUviatheArmV7Large
PhysicalAddressExtensions(LPAE).
(3) DCAN1hasonepinmuxoptionthatcanoptionallybeusedforMCANfunctionality.DCAN2hastwopinmuxoptions,oneofwhichcan
beoptionallyusedforMCANfunctionality.
(4) WideDynamicRangeandLensDistortionCorrection.
(5) FormoredetailsabouttheCTRL_WKUP_STD_FUSE_DIE_ID_2registerandBasePNbitfield,seetheTDA2PxTechnicalReference
Manual.
(6) X577Pxisthebasepartnumberforthesupersetdevice.Softwareshouldconstrainthefeaturesusedtomatchtheintendedproduction
device.TheBasePNregisterbitfieldvalueis0x69.
3.2 Related Products
AutomotiveProcessors
TDAxADASSoCs TI's TDAx Driver Assistance System-on-Chip (SoC) family offers scalable and open
solutions and a common hardware and software architecture for Advanced Driver Assistance
Systems (ADAS) applications including camera-based front (mono and stereo), rear,
surround view and night vision systems, and mid- and long-range radar and sensor fusion
systems.
CompanionProductsforTDA2 Review products that are frequently purchased or used in conjunction
withthisproduct.
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4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and are used in
conjunctionwithTable4-1throughTable 4-27tolocatesignalnamesandballgridnumbers.
Figure4-1.ABZS-PBGA-N760Package(Bottom View)
NOTE
The following bottom balls are not connected: AF7 / AF10 / AF13 / AF16 / AF19 / AE4 /
AE25/AB26/W3/W26/T3/T26/N3/N26/K3/K26/G3/D4/D25/C10/C13/C16/
C19/C22.
Theseballsdonotexistonthepackage.
4.2 Pin Attributes
Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describesthetablecolumnheaders:
1. BALL NUMBER:Ballnumber(s)onthebottom sideassociatedwitheachsignalonthebottom.
2. BALL NAME:Mechanicalnamefrompackagedevice(nameistakenfrommuxmode0).
3. SIGNAL NAME:Namesofsignalsmultiplexed oneachball(alsonoticethat thenameoftheballisthe
signalnameinmuxmode0).
NOTE
Table 4-1 does not take into account the subsystem multiplexing signals. The subsystem
multiplexingsignalsaredescribedinSection4.3,SignalDescriptions.
NOTE
IntheDriveroffmode,thebufferisconfiguredinhigh-impedance.
4. PHxx:ThiscolumnshowsifthefunctionalityisapplicableforTDA2PHxxdevices.
NotethatthePinAttributestablepresentsthefunctionalityof TDA2PSxxdevice.
PHxx-TDA2PHGx;TDA2PHFx;TDA2PHVx;TDA2PHAx;
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5. MUXMODE:Multiplexingmodenumber:
a. MUXMODE0istheprimarymode;thismeansthat whenMUXMODE=0,thefunctionmapped on
thepincorrespondstothenameofthepin. Theprimarymuxmodeisnotnecessarilythedefault
muxmode.
NOTE
The defaultmuxmodeis themode at thereleaseof thereset;also see theRESETREL.
MUXMODEcolumn.
b. MUXMODE1through15arepossiblemuxmodesfor alternatefunctions.Oneachpin, some
muxmodesareeffectivelyusedfor alternatefunctions,whilesomemuxmodesarenotused. Only
MUXMODEvalueswhichcorrespondtodefinedfunctionsshouldbeused.
c. AnemptyboxmeansNotApplicable
6. TYPE:Signaltypeanddirection:
– I=Input
– O=Output
– IO=InputorOutput
– D=Opendrain
– DS=DifferentialSignaling
– A=Analog
– PWR=Power
– GND=Ground
– CAP=LDOCapacitor
7. BALL RESET STATE: Thestateoftheterminalatpower-onreset:
– drive0(OFF):ThebufferdrivesV (pulldownorpullupresistornotactivated)
OL
– drive1(OFF):ThebufferdrivesV (pulldownorpullupresistornotactivated)
OH
– OFF:High-impedance
– PD:High-impedancewithanactivepulldownresistor
– PU:High-impedancewithanactivepullupresistor
– AnemptyboxmeansNotApplicable
8. BALL RESET REL.STATE: Thestateoftheterminalatthedeactivationoftherstoutnsignal(also
mappedtothePRCMSYS_WARM_OUT_RSTsignal)
– drive0(OFF):ThebufferdrivesV (pulldownorpullupresistornotactivated)
OL
– driveclk(OFF):Thebufferdrivesatogglingclock(pulldownorpullupresistornotactivated)
– drive1(OFF):ThebufferdrivesV (pulldownorpullupresistornotactivated)
OH
– OFF:High-impedance
– PD:High-impedancewithanactivepulldownresistor
– PU:High-impedancewithanactivepullupresistor
– AnemptyboxmeansNotApplicable
NOTE
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power Reset and Clock Management / PRCM Reset Management Functional
DescriptionsectionoftheDeviceTRM.
9. RESETREL.MUXMODE: Thismuxmodeisautomaticallyconfiguredatthereleaseoftherstoutn
signal(alsomappedtothePRCMSYS_WARM_OUT_RSTsignal).
AnemptyboxmeansNotApplicable.
10. IOVOLTAGEVALUE:ThiscolumndescribestheIO voltagevalue(thecorrespondingpowersupply).
AnemptyboxmeansNotApplicable.
11. POWER: ThevoltagesupplythatpowerstheterminalIO buffers.
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