TAS576xM 2x50W/4Ω PurePath™ Smart Amp

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TAS5766M,TAS5768M
ZHCSDC1D–SEPTEMBER2013–REVISEDOCTOBER2018
TAS576xM 2x50-W/4-Ω PurePath™智智能能放放大大器器
1 特特性性 2 应应用用
• PurePath智能放大器： • 音频接口盒
1
– 优化和保护动圈式扬声器 • 条形音箱
– 低音Q 补偿和频率扩展：音量更高、低音增 • 笔记本电脑
强、清晰度更佳且保真度更高。 • 一体化计算机
– 热量和偏移限制。 • 数字电视
• 立体声D类放大器：
3 说说明明
– 宽电源范围：4.5V 至26.4V
– 宽负载范围：2Ω至8Ω TAS576xMPurePath 智能放大器不仅可增强低音效果
– 高输出电流：2x7.5A 和音质保真度，还可提供更高的音量，同时将扬声器驱
– 峰值输出功率2x50W/4Ω 动至其热限值和机械限值。
– 连续功率：2x20W（不使用散热器） TAS576xM包含两个桥接负载(BTL) D类放大器，峰
– 电源、静音和待机开/关时无喀哒声和噼啪声 值功率高达2x50W/4Ω。在热保护方面，该放大器针对
– 低输出噪声：<60µVrms（12V 供电时）； 典型扬声器而设计，可处理扬声器音圈升温期间的高温
<90µVrms（24V 供电时）
峰值，然后将其平均功率降至安全限值。
– 低总谐波失真和噪声(THD+N)：<0.02%
（1W/4Ω、1kHz 时） 该器件具有4.5V至26.4V 宽电源范围，支持从双节锂
– 热保护、过流保护和短路保护 离子电池到固定24V电源各类不同的电源选项。
• 可配置的数字音频处理器。 凭借德州仪器(TI)的PurePathSmartAmp 技术，可
– 降频混频和具有10个BiQuad 的定制EQ 更多地以峰值功率（而非平均额定功率）来驱动扬声
• 数字音频接口：I2S或时分复用(TDM)输入 器，且不必担心因偏移或热过载而损坏扬声器。
– 44.1kHz 和48kHz快速(FS)
器器件件信信息息(1)
– 可配置的数字输出
器器件件编编号号 封封装装 封封装装尺尺寸寸（（标标称称值值））
• 多段数模转换器(DAC)，去抖动性能出色
• 集成高性能音频锁相环(PLL) TAS5766M HTSSOP(48) 12.50mmx6.10mm
• I2C控制 TAS5768M VQFN(48) 7.00mmx5.00mm
• 48引脚PowerPAD™散热薄型小外形尺寸 (1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
(HTSSOP)或超薄型四方扁平无引线(VQFN) 封装
智智能能放放大大器器概概览览
Smart SOA Smart Sense
System Inputs Sensor Inputs
Smart Amp
Adaptive Control Algorithm
Smart Enhance
DIN Volume Smart Bass, Smart Smart Protection AMP
EQ Thermal, Excursion
DRP
1
本文档旨在为方便起见，提供有关TI产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问www.ti.com，其内容始终优先。TI不保证翻译的准确
性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
EnglishDataSheet:SLAS965
TAS5766M,TAS5768M
ZHCSDC1D–SEPTEMBER2013–REVISEDOCTOBER2018 www.ti.com.cn
目目录录
1 特特性性.......................................................................... 1 7.5 Programming...........................................................36
2 应应用用.......................................................................... 1 7.6 RegisterMaps.........................................................38
3 说说明明.......................................................................... 1 8 ApplicationsandImplementation...................... 39
4 修修订订历历史史记记录录........................................................... 2 8.1 ApplicationInformation............................................39
8.2 TypicalApplications................................................40
5 PinConfigurationandFunctions......................... 3
9 PowerSupplyRecommendations...................... 47
6 Specifications......................................................... 6
9.1 AVDD,DVDD,CPVDDSupply...............................47
6.1 AbsoluteMaximumRatings......................................6
9.2 GVDDSupply..........................................................47
6.2 ESDRatings ............................................................6
9.3 PVCC,AVCCPowerSupply...................................47
6.3 RecommendedOperatingConditions.......................6
10 Layout................................................................... 48
6.4 ThermalInformation..................................................7
6.5 DCElectricalCharacteristics....................................7 10.1 LayoutGuidelines.................................................48
6.6 ACElectricalCharacteristics.....................................8 10.2 LayoutExamples...................................................49
6.7 ElectricalCharacteristics...........................................9 11 RegisterMapInformation................................... 51
6.8 TimingRequirements-I2CBusTiming..................10 11.1 DetailedRegisterMapDescriptions......................51
6.9 TypicalCharacteristics............................................11 12 器器件件和和文文档档支支持持..................................................... 75
7 DetailedDescription............................................ 16 12.1 相关链接................................................................75
7.1 Overview.................................................................16 12.2 商标....................................................................... 75
7.2 FunctionalBlockDiagram.......................................16 12.3 静电放电警告.........................................................75
7.3 FeatureDescription.................................................17 12.4 术语表................................................................... 75
7.4 DeviceFunctionalModes........................................20 13 机机械械、、封封装装和和可可订订购购信信息息....................................... 75
4 修修订订历历史史记记录录
注：之前版本的页码可能与当前版本有所不同。
ChangesfromRevisionC(September2014)toRevisionD Page
• Addedparagraphtoclarifythe3-wiremodeofI2Soperation.............................................................................................. 41
ChangesfromRevisionB(September2014)toRevisionC Page
• AddedNOTEandadditionaldescriptivetexttoApplicationsandImplementationsection. ................................................ 39
• MovedDetailedRegisterMapDescriptionssection ............................................................................................................ 51
ChangesfromRevisionA(June2014)toRevisionB Page
• AddeddescriptionsforCDST[5]throughCDST[0]inRegister94(Hex0x5E);andchangedBit6descriptionfrom
CDST[6:0]toCDST[6].......................................................................................................................................................... 69
ChangesfromOriginal(September2013)toRevisionA Page
• 将数据表更改为最新格式；将器件信息表添加到了第一页。.................................................................................................. 1
• 添加了TAS5768M器件.......................................................................................................................................................... 1
• 添加了RMT封装选项............................................................................................................................................................. 1
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5 Pin Configuration and Functions
RMTPackage
48-PinVQFN
TopView
R R L L
P R N R L N L P
D T P T N N T P T D
N U S U S S U S U N
G O B O B B O B O G
24 23 22 21 20 19 18 17 16 15
GND 25 14 GND
PVCC 26 13 PVCC
GVDD 27 12 AVCC
GAIN/FSW 28 11 FAULT
GND 29 10 GND
INNR 30 9 INNL
Thermal PAD
INPR 31 8 INPL
Connect to GND
DACR 32 7 DACL
AVDD 33 6 VNEG
GND 34 5 CAPM
SDA 35 4 GND
SCL 36 3 CAPP
GPIO1 37 2 CPVDD
GPIO2 38 1 DVDD
39 40 41 42 43 44 45 46 47 48
2 3 K K N K 1 P O D
DR PIO CL CL DI CL DR UV DO GN
A G S B R A T/ L
L M
S
X
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DCAPackage
48-PinHTSSOP
TopView
BSNR 1 48 BSNL
OUTNR 2 47 OUTNL
GND 3 46 GND
OUTPR 4 45 OUTPL
BSPR 5 44 BSPL
PVCC 6 43 PVCC
PVCC 7 42 PVCC
GVDD 8 41 AVCC
GAIN/FSW 9 40 FAULT
GND 10 39 GND
INNR 11 38 INNL
Thermal
INPR 12 PAD 37 INPL
DACR 13 Connect 36 DACL
to GND
AVDD 14 35 VNEG
GND 15 34 CAPM
SDA 16 33 GND
SCL 17 32 CAPP
GPIO1 18 31 CPVDD
GPIO2 19 30 DVDD
ADR2 20 29 GND
GPIO3 21 28 LDOO
SCLK 22 27 XSMT/UVP
BCLK 23 26 ADR1
DIN 24 25 LRCLK
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PinFunctions
SYMBOL HTTSOP VQFN TYPE(1) DESCRIPTION
PINNo. PINNo.
ADR1 26 45 I LSBaddressselectbitforI2C
ADR2 20 39 I 2ndLSBaddressselectbitforI2C
AVCC 41 12 PI AnalogSupply–connecttoPVCC
AVDD 14 33 PI AnalogSupply
BCLK 23 42 I Audiodatabitclockinput
BootstrapnegativeLeftchanneloutput,connectto220nFX7Rceramiccapto
BSNL 48 19 BST
OUTNL
BootstrapnegativeRightchanneloutput,connectto220nFX7Rceramiccapto
BSNR 1 20 BST
OUTNR
BootstrappositiveLeftchanneloutput,connectto220nFX7Rceramiccapto
BSPL 44 17 BST
OUTPL
BootstrappositiveRightchanneloutput,connectto220nFX7Rceramiccapto
BSPR 5 22 BST
OUTPR
CAPM 34 5 Chargepumpflyingcapacitorpinfornegativerail
CAPP 32 3 Chargepumpflyingcapacitorpinforpositiverail
CPVDD 31 2 PI Chargepumppowersupply,3.3V
DACL 36 7 O AnalogoutputfromDACleftchannel,groundcentered
DACR 13 32 O AnalogoutputfromDACRightchannel,groundcentered
DIN 24 43 I Audiodatainput
DVDD 30 1 PI Digitalpowersupply,3.3V
FAULT 40 11 OD Generalfaultreporting,OpenDrain,High=normaloperation,Low=faultcondition
GAIN/FSW 9 28 I SetspowerstageGainandselectsoutputswitchingfrequency
3,10,15, 4,10,14,15,
GND 29,33,39, 24,25,29,34, G Ground
46 48
GPIO1 18 37 I/O Generalpurposedigitalinputandoutputport
GPIO2 19 38 I/O Generalpurposedigitalinputandoutputport
GPIO3 21 40 I/O Generalpurposedigitalinputandoutputport
GVDD 8 27 PBY InternalGatedrivesupply,connect1uFtoGND
INNL 38 9 I NegativeaudioinputforLeftchannel.Internallybiasedat3V
INNR 11 30 I NegativeaudioinputforRightchannel.Internallybiasedat3V
INPL 37 8 I PositiveaudioinputforLeftchannel.Internallybiasedat3V
INPR 12 31 I PositiveaudioinputforRightchannel.Internallybiasedat3V
LDOO 28 47 PBY Internallogicsupplyrailpinfordecoupling,1.8V,connect1µFtoGND
LRCLK 25 44 I Audiodatawordclockinput
OUTNL 47 18 PO NegativeLeftchanneloutput
OUTNR 2 21 PO NegativeRightchanneloutput
OUTPL 45 16 PO PositiveLeftchanneloutput
OUTPR 4 23 PO PositiveRightchanneloutput
6,7,42,
PVCC 13,26 PI 4.5-Vto26.4-VPowersupply
43
SCL 17 36 I InputclockforI2C
SCLK 22 41 I Systemclockinput(alsoreferredtoasmasterclockinput)
SDA 16 35 I/O InputdataforI2C
Thermal
49 49 G ConnectThermalPadtoGround
pad
VNEG 35 6 PO Negativechargepumprailpinfordecoupling–3.3V
XSMT/UVP 27 46 I Softmutecontrol:Softmute(Low)/softun-mute(High)
(1) TYPE:BST=BootStrap,PO=PowerOutput,G=GeneralGround,I=Input,O=Output,I/O=InputorOutput,,PBY=PowerBypass,,
PI=PowerInput,.
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6 Specifications
6.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
MIN MAX UNIT
SupplyVoltage:PVCC,AVCC –0.3 30 V
V
CC
AVDD,DVDD,CPVDD –0.3 3.9 V
InputVoltage:INPL,INNL,INPR,INNR –0.3 6.3 V
V InputVoltage:GAIN/FSW,FAULT –0.3 GVDD+0.3 V
I
DigitalInputVoltage:DVDD=3.3V –0.3 3.9 V
T Operatingfree-airtemperature –40 85 °C
A
OperatingJunctiontemperature,digitaldie –40 125 °C
T
J
OperatingJunctiontemperature,powerdie –40 150 °C
Storagetemperature,T –40 125 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended
OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
6.2 ESD Ratings
VALUE UNIT
Humanbodymodel(HBM),perANSI/ESDA/JEDECJS- ±2000
V (1) Electrostatic 001,allpins(2) V
(ESD) discharge Chargeddevicemodel(CDM),perJEDECspecification ±500
JESD22-C101,allpins(3)
(1) Electrostaticdischarge(ESD)measuresdevicesensitivityandimmunitytodamagecausedbyassemblylineelectrostaticdischargesin
tothedevice.
(2) LevellistedaboveisthepassinglevelperANSI,ESDA,andJEDECJS-001.JEDECdocumentJEP155statesthat500-VHBMallows
safemanufacturingwithastandardESDcontrolprocess.
(3) LevellistedaboveisthepassinglevelperEIA-JEDECJESD22-C101.JEDECdocumentJEP157statesthat250-VCDMallowssafe
manufacturingwithastandardESDcontrolprocess.
6.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN TYP MAX UNIT
Vcc PVCC,AVCC 4.5 26.4
SupplyVoltage V
Vdd AVDD,DVDD,CPVDD 3 3.3 3.6
V Highlevelinputvoltage 2 V
IH
V Lowlevelinputvoltage 0.8 V
IL
V Lowleveloutputvoltage FAULT,R =100kΩ,PVCC=26V 0.8 V
OL pullup
PVCC=24V 3.2 4
PVCC=18V 2.5 3
R Minimumloadimpedance Ω
L
PVCC=12V 1.8 2
PVCC=6V 0.9 1
PVCC=24V 1.8 2.2
PBTLMinimumload PVCC=18V 1.4 1.6
R Ω
L_PBTL impedance PVCC=12V 1.0 1.2
PVCC=6V 0.5 0.6
Lo Outputfilterinductance Minimumoutputfilterinductanceundershort-circuitcondition 1 4.7 µH
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6.4 Thermal Information
TAS576xM
THERMALMETRIC(1) RMT(48PINS) DCA(48PINS) UNIT
4LAYERPCB(2) 2PLCABY(E3)R
R Junction-to-ambientthermalresistance 30 30
θJA
R Junction-to-case(top)thermalresistance 15 14
θJC(top)
R Junction-to-boardthermalresistance 6 13
θJB
°C/W
ψ Junction-to-topcharacterizationparameter 0.2 0.6
JT
ψ Junction-to-boardcharacterizationparameter 6 13
JB
R Junction-to-case(bottom)thermalresistance 1.9 0.7
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
(2) ForthePCBlayoutseetheTAS576xMRMTEVMUserGuide.A4layer60x60mm1ocPCBwasused
(3) ForthePCBlayoutseetheTAS576xMDCAEVMUserGuide.A2layer60x60mm1ocPCBwasused
6.5 DC Electrical Characteristics
AllspecificationsatT =25°C,AVDD=CPVDD=DVDD=3.3V,f =48kHz,systemclock=512f and24-bitdata,V =
A S S CC
12Vto24V,R =4Ω(unlessotherwisenoted)
L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Class-Doutputoffsetvoltage(measured PV =12V,gainsetto14dB 1 10 mV
CC
|VOS| differentially)
InputisBipolarZerodata PVCC=24V,gainsetto20dB 1.5 15 mV
Drain-sourceon-stateresistance,measured
R VCC=24V,I =500mA,T =25°C 120 mΩ
DS(on) pintopin out J
Gainpinvoltage<3V 13 14 15 dB
G AnalogGainfromINxxtoOUTxx
Gainpinvoltage>3.3V 19 20 21 dB
t Turn-ontime XSMT=2V 1.5 ms
on
t Turn-offtime XSMT=0.8V 0.8 ms
OFF
GVDD GateDriveSupplyVoltage IGVDD≤200µA 6.9 V
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6.6 AC Electrical Characteristics
AllspecificationsatT =25°C,AVDD=CPVDD=DVDD=3.3V,f =48kHz,systemclock=512f and24-bitdata,V =
A S S CC
12Vto24V,R =4Ωunlessotherwisenoted
L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
KSVR Powersupplyripplerejection 2si0g0namlVPPrippleat1kHz,gain=20dB,zeroinput –60 dB
THD+N=10%,1kHz,24-Vsupply,8-Ωload 30 W
PO Peakoutputpower
THD+N=10%,1kHz,24-Vsupply,4-Ωload 50 W
Ra=100kΩ,Rb=open 8
OutputswitchfrequencymultipleofFSGain Ra=20kΩ,Rb=100kΩ 10
Fsw setto14dB Ra=39kΩ,Rb=100kΩ 12
Ra=47kΩ,Rb=75kΩ 16
Ra=51kΩ,Rb=51kΩ 8
OutputswitchfrequencymultipleofFSGain Ra=75kΩ,Rb=47kΩ 10
Fsw setto20dB Ra=100kΩ,Rb=39kΩ 12
Ra=100kΩ,Rb=20kΩ 16
1W,1kHz,4Rload,12Vsupply 0.05%
THD+N TotalHarmonicDistortion+Noise
1W,1kHz,8Rload,24Vsupply 0.05%
20-22kHz,A-weighted,14dBgain,12Vsupply 60 µV
VN Outputintegratednoise
20-22kHz,A-weighted,20dBgain,24Vsupply 85 µV
20-22kHz,A-weighted,14dBgain,12Vsupply 103 dB
SNR SignaltoNoiseRatio
20-22kHz,A-weighted,20dBgain,24Vsupply 106 dB
Crosstalk VO=1Vrms,20dBgain,1kHz,4-Ωload –90 dB
IP Peakoutputcurrent 1kHz,10ms,3-Ωload,24-Vsupply 7.5 A
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6.7 Electrical Characteristics
AllspecificationsatT =25°C,AVDD=CPVDD=DVDD=3.3V,f =48kHz,systemclock=512f and24-bitdata,V =
A S S CC
12Vto24V,R =4Ω(unlessotherwisenoted)
L
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Resolution 16 24 32 Bits
DATAFORMAT(PCMMODE)
I2S,leftjustified,rightjustified
Audiodatainterfaceformat
andTDM
Audiodatabitlength 16,24,32-bitacceptable
Audiodataformat MSBFirst,2sComplement
f Samplingfrequency 8 48 kHz
S
CLOCKS
64,128,192,256,384,512,
Systemclockfrequency 768,1024,1152,1536,2048,or
3072F ,upto50MHz
SCLK
PLLinputfrequency/SCLClock ClockdividerusesfractionaldivideD>0,P=1 6.7 20 MHz
Frequency400kHz) ClockdividerusesintegerdivideD=0,P=1 1 20 MHz
DIGITALINPUT/OUTPUT
LogicFamily:3.3VLVCMOScompatible
V Highlevelinputvoltage 0.7xDV V
IH DD
0.3x
V lowlevelinputvoltage V
IL DV
DD
I Highlevelinputcurrent V =V 10 µA
IH IN DD
I lowlevelinputcurrent V =0V –10 µA
IL IN
V Highleveloutputvoltage I =–4mA 0.8xDV V
OH OH DD
0.22x
V lowleveloutputvoltage I =4mA V
OL OL DV
DD
DACDYNAMICPERFORMANCE,MEASUREDONDACLandDACR
THD+Nat–1dB –90 dB
Dynamicrange 109 dB
Signaltonoiseratio 109 dB
Channelseparation 109 dB
DACANALOGOUTPUT,MEASUREDONDACLandDACR
Outputvoltage 2.1 Vrms
Gainerror |%|ofFSR 2% 6%
Gainmismatch,channeltochannel |%|ofFSR 1/2% 6%
Bipolarzeroerror |Atbipolarzero| 1 5 mV
POWERSUPPLYREQUIREMENTS
DV DigitalSupplyVoltage 3 3.3 3.6 V
DD
AV AnalogSupplyVoltage 3 3.3 3.6 V
DD
Charge-pumpsupplyvoltage 3 3.3 3.6 V
f =48kHz,InputisBipolarZerodata 12 15 mA
s
I DV supplycurrentat3.3V f =48kHz,Inputis1kHz-1dBFSdata 12 15 mA
DD DD s
f =N/A,powerDownMode 0.5 0.8 mA
s
f =48kHz,InputisBipolarZerodata 11 16 mA
s
AVDD/CPVDDsupplycurrentat
f =48kHz,Inputis1kHz-1dBFSdata 24 32 mA
3.3V s
I f =N/A,powerDownMode 0.2 0.4 mA
CC s
XSMT=2V,noload,PV =12V 20 35 mA
CC
PVCCQuiescentsupplycurrent
XSMT=2V,noload,PV =24V 32 50 mA
CC
PVCCQuiescentsupplycurrentin XSMT=0.8V,noload,PVCC=12V 30 µA
I
CC(SD) shutdownmode XSMT=0.8V,noload,PV =24V 50 400 µA
CC
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6.8 Timing Requirements - I2C Bus Timing
MIN MAX UNIT
Standard 100
t SCLclockfrequency kHz
SCL
Fast 400
Standard 4.7
t BusfreetimebetweenaSTOPandSTARTcondition µs
BUF
Fast 1.3
Standard 4.7
t LowperiodoftheSCLclock µs
LOW
Fast 1.3
Standard 4
t HighperiodoftheSCLclock µs
HI
Fast 0.6
Standard 4.7
t Setuptimefor(repeated)STARTcondition µs
RS-SU
Fast 0.6
t Standard 4
S-HD
Holdtimefor(repeated)STARTcondition µs
t Fast 0.6
RS-HD
Standard 0.25
t Datasetuptime µs
D-SU
Fast 0.1
Standard 0 0.9
t Dataholdtime µs
D-HD
Fast 0 0.9
Standard 20+0.1C 1
B
t RisetimeofSCLsignal µs
SCL-R
Fast 20+0.1C 0.3
B
RisetimeofSCLsignalafterarepeatedSTARTconditionandafteran Standard 20+0.1CB 1
t µs
SCL-R1 acknowledgebit Fast 20+0.1C 0.3
B
Standard 20+0.1C 1
B
t FalltimeofSCLsignal µs
SCL-F
Fast 20+0.1C 0.3
B
Standard 20+0.1C 1
B
t RisetimeofSDAsignal µs
SDA-R
Fast 20+0.1C 0.3
B
Standard 20+0.1C 1
B
t FalltimeofSDAsignal µs
SDA-F
Fast 20+0.1C 0.3
B
Standard 4
t SetuptimeforSTOPcondition µs
P-SU
Fast 0.6
C CapacitiveloadforSDAandSCLline 400 pF
B
t Pulsewidthofspikesuppressed Fast 50 ns
SP
Noisemarginathighlevelforeachconnecteddevice(including
V 0.2V V
NH hysteresis) DD
Figure1. RegisterAccessTiming
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