TAS5717 / TAS5719 Digital-Input Stereo Amplifier With Integrated CAP-Free HP Amp

69 Pages·2016·1.38 MB·English

TAS5717
TAS5719
www.ti.com SLOS655A–NOVEMBER2010–REVISEDFEBRUARY2011
10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier
CheckforSamples:TAS5717,TAS5719
FEATURES
1
• AudioInput/Output • Benefits
2
– TAS5717Supports2×10Wand TAS5719 – EQ:SpeakerEqualizationImproves Audio
Supports2×15WOutput Performance
– WidePVDDRange,From 4.5Vto26V – DRC:DynamicRangeCompression.Can
– EfficientClass-DOperationEliminates BeUsedAsPowerLimiter. Enables
NeedforHeatsinks SpeakerProtection, EasyListening,
Night-ModeListening
– RequiresOnly3.3VandPVDD
– DirectPathTechnology:Eliminates Bulky
– OneSerialAudioInput(TwoAudio
DCBlockingCapacitors
Channels)
– StereoHeadphone/StereoLineDrivers:
– I2CAddressSelectionviaPIN(ChipSelect)
Adjust GainviaExternalResistors,
– Supports8-kHzto48-kHzSampleRate
DedicatedActiveHeadponeMutePin,High
(LJ/RJ/I2S)
Signal-to-Noise Ratio
– ExternalHeadphone-AmplifierShutdown
– Two-BandDRC:SetTwoDifferent
Signal
ThresholdsforLow-andHigh-Frequency
– IntegratedCAP-FreeHeadphoneAmplifier Content
– Stereo Headphone(Stereo2-V RMSLine
Driver)Outputs DESCRIPTION
• Audio/PWMProcessing The TAS5717/TAS5719 is a 10-W/15-W, efficient,
– IndependentChannelVolumeControlsWith digital audio-power amplifier for driving stereo
24-dBtoMute bridge-tied speakers. One serial data input allows
processing of up to two discrete audio channels and
– ProgrammableTwo-BandDynamicRange
seamless integration to most digital audio processors
Control
and MPEG decoders. The device accepts a wide
– 14ProgrammableBiquadsforSpeaker EQ range of input data and data rates. A fully
– ProgrammableCoefficientsfor DRC Filters programmable data path routes these channels to the
internalspeakerdrivers.
– DCBlockingFilters
– 0.125-dBFineVolumeSupport The TAS5717/9 is a slave-only device receiving all
clocksfromexternalsources. TheTAS5717/TAS5719
• GeneralFeatures
operates with a PWM carrier between a 384-kHz
– SerialControlInterfaceOperationalWithout switching rate and a 352-KHz switching rate,
MCLK depending on the input sample rate. Oversampling
– Factory-TrimmedInternalOscillatorfor combined with a fourth-order noise shaper provides a
flat noise floor and excellent dynamic range from
AutomaticRateDetection
20Hzto20kHz.
– SurfaceMount, 48-Pin,7-mm× 7-mm
HTQFPPackage
– AD,BD,andTernaryPWM-ModeSupport
– Thermaland Short-CircuitProtection
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
FilterProisatrademarkofTexasInstruments.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. ©2010–2011,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
TAS5717
TAS5719
SLOS655A–NOVEMBER2010–REVISEDFEBRUARY2011 www.ti.com
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V 4.5 V–26 V
AVDD/DVDD/ PVDD
HP_VDD
OUT_A
LRCLK
Digital SCLK BST_A
Audio
Source MCLK LCBTL
BST_B
SDIN
OUT_B
2 SDA OUT_C
I C
Control SCL
BST_C
LC
BTL
Control RESET BST_D
Inputs
PDN
OUT_D
PLL_FLTP
Loop
Filter(1)
PLL_FLTM
HPL_OUT
HPL_IN HPR_OUT
Headphone IN
(Single-Ended)
HPL_OUT
HP_SD
B0264-13
(1)SeetheTAS5717/9User'sGuideforloop-filtervalues.
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FUNCTIONAL VIEW
OUT_A
2´HB
Serial 4th FETOut OUT_B
SDIN Audio S Order
Port DigitalAudio Processor R Noise
(DAP) C Shaper
and OUT_C
PWM 2´HB
FETOut
OUT_D
Protection
Logic
MCLK Sample Rate ClicCk oanntdro Plop
SCLK Autodetect
LRCLK and PLL
Microcontroller
SDA Serial Based
Control System
SCL Control
Terminal Control
HPL_IN HPL_OUT
HPR_IN HPR_OUT
Charge Pump
HeadphoneAmp/Line Driver
B0262-08
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DAP PROCESS STRUCTURE
24 24 B0321-11
p24 p24 el) vel)
cli cli ev Le
Left L Right
LevelMeter 32 32Bit- 2 Bit-
2IC:56VDISTA32 32 2IC:57VDISTB 32 2IC:0x6B (2IC:0x6C (3
1] 0] 1] 0]
1[ 1[ 2[ 2[
5 5 5 5
x x x x
0 0 0 0
0] 1]
6[ 6[
4 4
x x
0 0
E
Vol1 Vol2 Vol Vol g 0x0
e
d R
n Re GL GL nfig
dress i A A Vol Co
d
a
b
u
S
C m1
2I 2i
v
0 1 4 5
7 7 7 7
0x 0x 0x 0x
59 Q 5D Q 5F Q 5B Q
58, 2B 5C, 2B 5E, 2B 5A, 2B
2F Q 39 Q
– B – B
27 9 31 9
2 3 6 7
7 7 7 7
x x x x
0 0 0 0
Q Q
26 B 30 B
1 1
L R
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PIN ASSIGNMENT AND DESCRIPTIONS
PHPPackage
(Top View)
ML MR AB AB CD
_PW _PW DD_ T_A T_A ND_ T_B T_B T_C T_C ND_ T_D
P P V S U G U S S U G U
H H P B O P O B B O P O
48 47 46 45 44 43 42 41 40 39 38 37
HPL_IN 1 36 BST_D
HPL_OUT 2 35 PVDD_CD
HPR_OUT 3 34 GVDD_OUT
HPR_IN 4 33 HP_SD
HPVSS 5 32 SSTIMER
CPN 6 TAS5717 31 VREG
CPP 7 (TAS5719) 30 AGND
HPVDD 8 29 GND
AVSS 9 28 DVSS
PLL_FLTM 10 27 DVDD
PLL_FLTP 11 26 STEST
VR_ANA 12 25 RESET
13 14 15 16 17 18 19 20 21 22 23 24
D L K S O G N K K N A L
AVD A_SE MCL SC_RE DVSS VR_DI PD LRCL SCL SDI SD SC
O
P0075-11
PINFUNCTIONS
PIN TYPE(1) 5-V TERMINATION(2) DESCRIPTION
NAME NO. TOLERANT
AGND 30 P Analoggroundforpowerstage
A_SEL 14 DIO ThispinismonitoredontherisingedgeofRESET.Avalueof0
makestheI2Cdevaddress0x54,andavalueof1makesit0x56.
AVDD 13 P 3.3-Vanalogpowersupply
AVSS 9 P Analog3.3-Vsupplyground
BST_A 45 P High-sidebootstrapsupplyforhalf-bridgeA
BST_B 41 P High-sidebootstrapsupplyforhalf-bridgeB
BST_C 40 P High-sidebootstrapsupplyforhalf-bridgeC
BST_D 36 P High-sidebootstrapsupplyforhalf-bridgeD
CPN 6 IO Charge-pumpflying-capacitornegativeconnection
CPP 7 IO Charge-pumpflying-capacitorpositiveconnection
DVDD 27 P 3.3-Vdigitalpowersupply
DVSS 28 P Digitalground
DVSSO 17 P Oscillatorground
GND 29 P Analoggroundforpowerstage
(1) TYPE:A=analog;D=3.3-Vdigital;P=power/ground/decoupling;I=input;O=output
(2) Allpullupsareweakpullupsandallpulldownsareweakpulldowns.Thepullupsandpulldownsareincludedtoassureproperinputlogic
levelsifthepinsareleftunconnected(pullups→logic1input;pulldowns→logic0input).
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PINFUNCTIONS(continued)
PIN TYPE(1) 5-V TERMINATION(2) DESCRIPTION
NAME NO. TOLERANT
GVDD_OUT 34 P Gatedriveinternalregulatoroutput
HPL_IN 1 AI HeadphoneleftIN(single-ended,analogIN)
HPL_OUT 2 AO HeadphoneleftOUT(single-ended,analogOUT)
HP_PWML 48 DO PWMleft-channelheadphoneout
HP_PWMR 47 DO PWMright-channelheadphoneout
HPR_IN 4 AI HeadphonerightIN(single-ended,analogIN)
HPR_OUT 3 AO HeadphonerightOUT(single-ended,analogOUT)
HP_SD 33 AI Headphoneshutdown(active-low)
HPVDD 8 P Headphonesupply
HPVSS 5 P Headphoneground
LRCLK 20 DI 5-V Pulldown Inputserialaudiodataleft/rightclock(samplerateclock)
MCLK 15 DI 5-V Pulldown Masterclockinput
OSC_RES 16 AO Oscillatortrimresistor.Connectan18-kΩ1%resistortoDVSSO.
OUT_A 44 O Output,half-bridgeA
OUT_B 42 O Output,half-bridgeB
OUT_C 39 O Output,half-bridgeC
OUT_D 37 O Output,half-bridgeD
PDN 19 DI 5-V Pullup Powerdown,active-low.PDNpreparesthedeviceforlossofpower
suppliesbyshuttingdownthenoiseshaperandinitiatingthePWM
stopsequence.
PGND_AB 43 P Powergroundforhalf-bridgesAandB
PGND_CD 38 P Powergroundforhalf-bridgesCandD
PLL_FLTM 10 AO PLLnegativeloop-filterterminal
PLL_FLTP 11 AO PLLpositiveloop-filterterminal
PVDD_AB 46 P Power-supplyinputforhalf-bridgeoutputA
PVDD_CD 35 P Power-supplyinputforhalf-bridgeoutputC
RESET 25 DI 5-V Pullup Reset,active-low.Asystemresetisgeneratedbyapplyingalogiclow
tothispin.RESETisanasynchronouscontrolsignalthatrestoresthe
DAPtoitsdefaultconditions,andplacesthePWMinthehard-mute
(high-impedance)state.
SCL 24 DI 5-V I2Cserialcontrolclockinput
SCLK 21 DI 5-V Pulldown Serialaudiodataclock(shiftclock).SCLKistheserialaudioportinput
databitclock.
SDA 23 DIO 5-V I2Cserialcontroldatainterfaceinput/output
SDIN 22 DI 5-V Pulldown Serialaudiodatainput.SDINsupportsthreediscrete(stereo)data
formats.
SSTIMER 32 AI ControlsramptimeofOUT_Xtominimizepop.Leavethispinfloating
forBDmode.Requirescapacitorof2.2nFtoGNDinADmode.The
capacitordeterminestheramptime.
STEST 26 DI Factorytestpin.ConnectdirectlytoDVSS.
VR_ANA 12 P Internallyregulated1.8-Vanalogsupplyvoltage.Thispinmustnotbe
usedtopowerexternaldevices.
VR_DIG 18 P Internallyregulated1.8-Vdigitalsupplyvoltage.Thispinmustnotbe
usedtopowerexternaldevices.
VREG 31 P Digitalregulatoroutput.Nottobeusedforpoweringexternalcircuitry.
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ABSOLUTE MAXIMUM RATINGS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
VALUE UNIT
DVDD,AVDD,HPVDD –0.3to3.6 V
Supplyvoltage
PVDD_X –0.3to30 V
HPL_IN,HPR_IN –0.3to4.2 V
3.3-Vdigitalinput –0.5toDVDD+0.5 V
Inputvoltage
5-Vtolerant(2)digitalinput(exceptMCLK) –0.5toDVDD+2.5(3) V
5-VtolerantMCLKinput –0.5toAVDD+2.5(3) V
OUT_xtoPGND_x 22(4) V
BST_xtoPGND_x 32(4) V
Inputclampcurrent,I ±20 mA
IK
Outputclampcurrent,I ±20 mA
OK
Operatingfree-airtemperature 0to85 °C
Operatingjunctiontemperaturerange 0to150 °C
Storagetemperaturerange,T –40to125 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsarenotimplied.Exposuretoabsolute-maximumconditionsforextendedperiodsmayaffectdevicereliability.
(2) 5-VtolerantinputsarePDN,RESET,SCLK,LRCLK,MCLK,SDIN,SDA,andSCL.
(3) Maximumpinvoltageshouldnotexceed6V.
(4) DCvoltage+peakacwaveformmeasuredatthepinshouldbebelowtheallowedlimitforallconditions.
THERMAL INFORMATION
TAS5717
THERMALMETRIC(1) PHP UNIT
48PINS
θ Junction-to-ambientthermalresistance(2) 35.2 °C/W
JA
θ Junction-to-boardthermalresistance(3) 10.9 °C/W
JB
θ Junction-to-case(bottom)thermalresistance(4) 1.6 °C/W
JC(bottom)
θ Junction-to-case(top)thermalresistance(5) 19.7 °C/W
JC(top)
ψ Junction-to-topcharacterizationparameter(6) 3.4 °C/W
JT
ψ Junction-to-boardcharacterizationparameter(7) 10.1 °C/W
JB
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
(2) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,as
specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a.
(3) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB
temperature,asdescribedinJESD51-8.
(4) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific
JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
(5) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.Nospecific
JEDEC-standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
(6) Thejunction-to-topcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted
JT
fromthesimulationdataforobtainingθ ,usingaproceduredescribedinJESD51-2a(sections6and7).
JA
(7) Thejunction-to-boardcharacterizationparameter,ψ ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted
JB
fromthesimulationdataforobtainingθ ,usingaproceduredescribedinJESD51-2a(sections6and7).
JA
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RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Digital/analogsupplyvoltage DVDD,AVDD 3 3.3 3.6 V
Half-bridgesupplyvoltage PVDD_X 4.5 V
V High-levelinputvoltage 5-Vtolerant 2 V
IH
V Low-levelinputvoltage 5-Vtolerant 0.8 V
IL
T Operatingambienttemperaturerange 0 85 °C
A
T (1) Operatingjunctiontemperaturerange 0 125 °C
J
R (BTL) Loadimpedance Outputfilter:L=15μH,C=680nF 4 8 Ω
L
Minimumoutputinductanceunder 4.7
L (BTL) Output-filterinductance μH
O short-circuitcondition
(1) Continuousoperationabovetherecommendedjunctiontemperaturemayresultinreducedreliabilityand/orlifetimeofthedevice.
RECOMMENDED OPERATING CONDITIONS FOR HEADPHONE/LINE DRIVER
MIN NOM MAX UNIT
Digital/analogsupplyvoltage HPVDD 3 3.3 3.6 V
Headphone-modeloadimedance 16
R_hp_L 32 Ω
(HPL/HPR)
Line-diver-modeloadimpedance 0.6
R_ln_L 10 kΩ
(HPL/HPR)
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER TESTCONDITIONS VALUE UNIT
11.025/22.05/44.1-kHzdatarate±2% 352.8 kHz
Outputsamplerate
48/24/12/8/16/32-kHzdatarate±2% 384
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
f MCLKFrequency 2.8224 24.576 MHz
MCLKI
MCLKdutycycle 40% 50% 60%
tr/
Rise/falltimeforMCLK 5 ns
tf
(MCLK)
LRCLKallowabledriftbeforeLRCLKreset 4 MCLKs
ExternalPLLfiltercapacitorC1 SMD0603Y5V 47 nF
ExternalPLLfiltercapacitorC2 SMD0603Y5V 4.7 nF
ExternalPLLfilterresistorR SMD0603,metalfilm 470 Ω
Fcp ChargePumpSwitchingFrequency 500 700 KHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics
TA=25°,PVCC_X=13V,DVDD=AVDD=3.3V,R =8Ω,BTLADMode,f =48KHz(unlessotherwisenoted)
L S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
V High-leveloutputvoltage FAULTZandSDA I =–4mA 2.4 V
OH OH
DVDD=3V
V Low-leveloutputvoltage FAULTZandSDA I =4mA 0.5 V
OL OL
DVDD=3V
V <V ;DVDD=AVDD 75
I Low-levelinputcurrent I IL μA
IL =3.6V
V >V ;DVDD= 75
I High-levelinputcurrent I IH μA
IH AVDD=3.6V
Normalmode 48 70
3.3Vsupplyvoltage(DVDD,
IDD 3.3Vsupplycurrent AVDD) Reset(RESET=low, 21 32 mA
PDN=high)
Normalmode 20 34
IPVDD Half-bridgesupplycurrent Noload(PVDD_X) Reset(RESET=low, 5 13 mA
PDN=high)
Drain-to-sourceresistance,LS T =25°C,includesmetallizationresistance 200
J
rDS(on) (1) Drain-to-sourceresistance, mΩ
T =25°C,includesmetallizationresistance 200
HS J
I/OProtection
V Undervoltageprotectionlimit PVDDfalling 3.5 V
uvp
V Undervoltageprotectionlimit PVDDrising 4.5 V
uvp,hyst
OTE(2) Overtemperatureerror 150 °C
OTE (2) Extratemperaturedrop 30 °C
HYST requiredtorecoverfromerror
I Overcurrentlimitprotection 4.5 A
OC
I Overcurrentresponsetime 150 ns
OCT
Internalpulldownresistorat Connectedwhendriversaretristatedtoprovidebootstrap
R 3 kΩ
PD theoutputofeachhalf-bridge capacitorcharge.
(1) Thisdoesnotincludebond-wireorpinresistance.
(2) Specifiedbydesign
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AC Characteristics (BTL)
PVDD_X=12V,BTLADmode,f =48KHz,R =8Ω,audiofrequency=1kHz,(unlessotherwisenoted).Allperformance
S L
isinaccordancewithrecommendedoperatingconditions,unlessotherwisespecified.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
PVDD=13V,10%THD,1-kHzinput
10
signal
P Poweroutputperchannel PVDD=8V,10%THD,1-kHzinputsignal 4.1 W
O
PVDD=18V,10%THD,1-kHzinput 15(1)
signal
PVDD=13V;P =1W 0.13%
O
THD+N Totalharmonicdistortion+noise
PVDD=8V;P =1W 0.2%
O
V Outputintegratednoise(rms) A-weighted 56 μV
n
P =0.25W,f=1kHz(BDmode) –82
O
Crosstalk dB
P =0.25W,f=1kHz(ADmode) –69
O
SNR Signal-to-noiseratio (2) A-weighted,f=1kHz,maximumpowerat –105 dB
THD<1%
(1) 15WissupportedonlyintheTAS5719.
(2) SNRiscalculatedrelativeto0-dBFSinputlevel.
AC Characteristics (Headphone/Line Driver)
PVDD_X=12V,BTLADmode,f =48KHz,R =8Ω,audiofrequency=1kHz,(unlessotherwisenoted).Allperformance
S L
isinaccordancewithrecommendedoperatingconditions,unlessotherwisespecified.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Po(hp) Headphonepoweroutputperchannel HP_VDD=3.3V(Rhp=32Ω;THD1%) 25 mW
HP_gain Headphonegain AdjustableviaRinandRfb
SNR_hp Sgnal-to-noiseratio(headphonemode) Rhp=32Ω 101 dB
SNR_ln Sgnal-to-noiseratio(linedrivermode) 2-Vrmsoutput 105 dB
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