SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling

394 Pages·2004·44.974 MB·English

by  Stuart Sutherland, Simon Davidmann, Peter Flake (auth.)

SystemVerilog
For Design
A Guide to Using SystemVerilog
for Hardware Design and Modeling
SystemVerilog
For Design
A Guide to Using SystemVerilog
for Hardware Design and Modeling
by
Stuart Sutherland
Simon Davidmann
Peter Flake
Foreword by Phil Moorby
~.
"
Springer-Science+Business Media, B.V.
•• Electronic Services <http://www.wkap.nl>
Library of Congress Cataloging-in-Publication
Title: SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware
Design and Modeling
Author (s): Stuart Sutherland, Simon Davidmann and Peter Flake
Foreword by Phil Moorby
ISBN 978-1-4757-6684-4 ISBN 978-1-4757-6682-0 (eBook)
DOI 10.1007/978-1-4757-6682-0
Copyright © 2004 by Springer Science+Business Media Dordrecht
Second Printing 2004.
Originally published by Kluwer Academic Publishers in 2004.
Softcover reprint ofthe hardcover 1st edition 2004
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, electronic, mechanical, photo-copying,
microfilming, recording, or otherwise, without the prior written permission ofthe publisher,
with the exception of any material supplied specifically for the purpose of being entered and
executed on a computer system, for exclusive use by the purchaser of the work.
Permissions forbooks published in the USA: permissions@wkap. com
Permissions for books published in Europe: [email protected]
Printed on acid-free paper.
Dedications
To mywonderfulwife, LeeAnn, andmychildren,Ammon, Tamara, Hannah, Sethand
Samuel-thankyoufor allyourpatienceduringthemanylonghoursandlatenights
whilewritingthisbook.
StuartSutherland
Portland, Oregon
To allofthestaffofCo-Design andthemanyEDAcolleaguesthatworkedwithme
overtheyears- thankyoufor helpingtoevolveVerilogandmakeitsextensionand
evolutionareality. AndtoPenny, EmmaandCharles- thankyoufor allowingme
thetimetoindulgeinlanguagedesign (andincarsandguitars...).
Simon Davidmann
SantaClara, California
TomywifeMonique,forsupportingmewhenIwasnotworking, andwhenIwas
workingtoomuch.
PeterFlake
Thame, UK
About the Authors
Stuart Sutherlandprovides expert instruction on using SystemVerilog and Verilog.
He has been involved in defining the Verilog language since the beginning ofIEEE
standardization work in 1993, and is a member of both the IEEE Verilog standards
committee (where heserves asco-chairoftheVerilogPLI task force),andtheAccel
lera SystemVerilog committee (where he serves as the editor for the SystemVerilog
Language Reference Manual). StuartSutherland hasmorethan 19yearsofexperience
in hardware design, and over 15years ofexperience with Verilog.He isthe founder
ofSutherlandHDLInc., whichspecializes inproviding expertHDL trainingservices.
He holds a Bachelors degree in Computer Science, with an emphasis in Electronic
Engineering Technology. He has also authored "The Verilog PLIHandbook" and
"Verilog-2001:A GuidetotheNewFeatures ofthe VerilogHDL".
Simon Davidmann has been involved with HDLs since 1978.He was a member of
theHILO teamatBrunei University intheUK.In 1984hebecame anASIC designer
and embedded software developer ofreal time professional musical instruments for
Simmons Percussion.In 1988,hebecame involvedwithVerilogasthefirstEuropean
employee ofGateway Design Automation. He founded Chronologie Simulation in
Europe, theEuropean officeofVirtual Chips(inSilicon), andthen theEuropean oper
ationsofAmbit Design. In 1998,heco-founded Co-Design Automation, andwasco
creator ofSUPERLOG. As CEO ofCo-Design, hewas instrumental intransitioning
SUPERLOG into Accellera asthe beginning ofSystemVerilog. Mr. Davidmann is a
member oftheAccellera SystemVerilogandIEEE 1364Verilog committees.Heisa
consultant to, and board member of, several technology and EDA companies, and is
Visiting ProfessorofDigital Systems atQueen Mary,UniversityofLondon.
Peter Flake wasaco-founderandChiefTechnical Officer atCo-DesignAutomation
andwasthe main architect oftheSUPERLOGlanguage. With the acquisition ofCo
Design by Synopsys in 2002, he became a Scientist at Synopsys. His EDA career
spans30years:hewasthelanguage architectandproject leaderoftheHILOdevelop
ment effort while atBrunei University in Uxbridge, U.K., and atGenRad.HILO was
the firstcommercialHDL-based simulation, faultsimulation andtiming analysis sys
tem ofthe early/mid 1980s.He holds a Master ofArts degree from Cambridge Uni
versity in the U.K. and has made many conference presentations on the subject of
HDLs.
Table ofContents
Foreword xxi
Preface xxiii
Targetaudience xxiii
Topicscovered xxiv
Abouttheexamplesinthisbook xxv
Obtainingcopiesoftheexamples xxvi
Exampletesting xxvi
Othersourcesofinformation xxvi
Acknowledgements xxviii
Chapter1:IntroductiontoSystemVerilog 1
1.1 SystemVerilogorigins 1
1.1.1 TheAccelleraSystemVerilogstandard 2
1.1.2 DonationstoSystemVerilog 3
1.2 KeySystemVerilogenhancementsforhardwaredesign .4
1.3 Summary 5
Chapter2:SystemVeriiogLiteralValuesandBuilt-inDataTypes 7
2.1 Enhancedliteralvalueassignments 8
2.2 •defineenhancements 9
2.2.1 Includingbackslashesinthemacrotext... 9
2.2.2 Includingquotesinthemacrotext.. 9
2.2.3 Constructingidentifiernamesfrommacros 10
2.3 Externalcompilationunitdeclarations ll
2.3.1 Synthesisguidelines 14
2.3.2 SystemVerilogidentifiersearchrules 15
2.3.3 Sourcecodeorder 15
2.3.4 Codingguidelinesforexternaldeclarations 16
2.4 Simulationtimeunitsandprecision 18
2.4.1 Verilog'stimescaledirective 18
2.4.2 Timevalueswithtimeunits 20
2.4.3 Module-leveltimeunitandprecision 21
2.4.4 Compilation-unittimeunitsandprecision 22
2.5 SystemVerilogdatatypes 24
2.5.1 Verilogdatatypes 24
2.5.2 SystemVeriiogdatatypes 25
2.5.3 Synthesisguidelines 27
2.6 Relaxationofdatatyperules 27
2.7 Signedandunsignedmodifiers 31
2.8 Staticandautomaticvariables 32
2.8.1 Staticandautomaticvariableinitialization 34
2.8.2 Synthesisguidelinesforautomaticvariables 37
2.8.3 Guidelinesforusingstaticandautomaticvariables 37
2.9 Deterministicvariableinitialization 38
2.9.1 Initializationdeterminism 38
2.9.2 Initializingsequentiallogicasynchronousinputs .41
2.10 Typecasting 43
2.10.1 Static(compiletime)casting .43
2.10.2 Dynamiccasting 44
2.10.3 Synthesisguidelines 45
2.11 Constants 46
2.12 Summary 47
Chapter3:SystemVerilogUser-Defined and EnumeratedDataTypes 49
3.1 User-definedtypes 49
3.1.1 Localtypedefdeclarations 50
3.1.2 Externaltypedefdeclarations 50
3.1.3 Namingconventionforuser-definedtypes 51
3.2 Enumerateddatatypes 52
3.2.1 Enumeratedtypenamesequences 55
3.2.2 Enumeratedtypenamescope 55
3.2.3 Enumeratedtypevalues 56
3.2.4 Datatypeofenumeratedtypevalues 57
3.2.5 Typedandanonymousenumerations 58
3.2.6 Strongtypingonenumeratedtypeoperations 58
3.2.7 Castingexpressionstoenumeratedtypes 60
3.2.8 Specialsystemtasksandmethodsforenumeratedtypes 61
3.2.9 Printingenumeratedtypes 63
3.3 Summary 64
Chapter4: SystemVeriiog Arrays,Structuresand Unions 65
4.1 Structures 66
4.1.1 Typedandanonymousstructures 67
4.1.2 Assigningvaluestostructures 68
4.1.3 Packedandunpackedstructures 70
x
4.1.4 Passingstructuresthroughports 73
4.1.5 Passingstructuresasargumentstotasksandfunctions 73
4.1.6 Synthesisguidelines 74
4.2 Unions 74
4.2.1 Typedandanonymousunions 75
4.2.2 Unpackedunions 75
4.2.3 Packedunions 76
4.2.4 Synthesisguidelines 78
4.2.5 Anexampleofusingstructuresandunions 78
4.3 Arrays 80
4.3.1 Unpackedarrays 80
4.3.2 Packedarrays 83
4.3.3 Usingpackedandunpackedarrays 85
4.3.4 Initializingarraysatdeclaration 86
4.3.5 Assigningvaluestoarrays 88
4.3.6 Copyingarrays 90
4.3.7 Copyingarraysusingbit-streamcasting 91
4.3.8 Arraysofarrays 92
4.3.9 Usinguser-definedtypeswitharrays 93
4.3.10 Passingarraysthroughportsandtotasksandfunctions 93
4.3.11 Arraysofstructuresandunions 94
4.3.12 Arraysinstructuresandunions 95
4.3.13 Synthesisguidelines 95
4.3.14 Anexampleofusingarrays 96
4.4 Arrayqueryingsystemfunctions 97
4.5 The$bits"sizeof'systemfunction 99
4.6 Dynamicarrays,associativearrays,sparsearraysandstrings 100
4.7 Summary 102
Chapter5:SystemVeriiogProceduralBlocks, Tasks and Functions 103
5.1 Veriloggeneralpurposealwaysproceduralblock 104
5.2 SystemVerilogspecializedproceduralblocks 108
5.2.1 Combinationallogicproceduralblocks 108
5.2.2 Latchedlogicproceduralblocks 115
5.2.3 Sequentiallogicproceduralblocks 117
5.2.4 Synthesisguidelines 118
5.3 Enhancementstotasksandfunctions 118
5.3.1 Staticandautomaticstorageintasksandfunctions 118
5.3.2 Implicittaskandfunctionstatementgrouping 119
5.3.3 Returningfunctionvalues 120
xi
5.3.4 Returningbeforetheendoftasksandfunctions 120
5.3.5 Voidfunctions 121
5.3.6 Passingtask/functionargumentsbyname 123
5.3.7 Enhancedfunctionformalarguments 124
5.3.8 Functionswithnoformalarguments 124
5.3.9 Defaultformalargumentdirectionandtype 125
5.3.10 Defaultformalargumentvalues 126
5.3.11 Arrays,structuresandunionsasformalarguments 127
5.3.12 Passingargumentvaluesbyreferenceinsteadofcopy 127
5.3.13 Namedtaskandfunctionends 131
5.3.14 Emptytasksandfunctions 131
5.4 Summary 132
Chapter6:SystemVerilogProceduralStatements 133
6.1 Newoperators 134
6.1.1 Incrementanddecrementoperators 134
6.1.2 Assignmentoperators 137
6.1.3 Equalityoperatorswithdon't carewildcards 140
6.1.4 Setmembershipoperator-inside 141
6.2 Operandenhancements 142
6.2.1 Operationson2-stateand4-statetypes 142
6.2.2 Castingexpressionsizes 143
6.2.3 Castingexpressionsignedness 144
6.3 Enhancedforloops 144
6.3.1 Localvariableswithinforloopdeclarations 145
6.3.2 Multipleforloopassigmnents 147
6.3.3 Hierarchicallyreferencingvariablesdeclaredinforloops 147
6.3.4 Synthesisguidelines 148
6.4 Bottomtestingdo whileloop 148
6.4.1 Synthesisguidelines 150
6.5 Newjumpstatements- break,continue,return 150
6.5.1 Thecontinuestatement 151
6.5.2 Thebreakstatement 152
6.5.3 Thereturnstatement 152
6.5.4 Synthesisguidelines 153
6.6 Enhancedblocknames 153
6.7 Statementlabels 156
6.8 Enhancedcasestatements 157
6.8.1 Uniquecasedecisions 157
6.8.2 Prioritycasestatements 160
xii