Systematic Design for Optimisation of Popelined ADCs

170 Pages·2003·12.25 MB·English

by  João Goes

SYSTEMATIC DESIGN FOR OPTIMISATION OF PIPELINED ADCs
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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SYSTEMATIC DESIGN
FOR OPTIMISATION
OF PIPELINED ADCs
by
João Goes
Universidade Nova de Lisboa, Portugal
João C. Vital
Chipidea – Microelectronics, SA., Portugal
and
José Franca
University of Lisbon, Portugal
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48193-6
Print ISBN: 0-7923-7291-3
©2003 Kluwer Academic Publishers
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Dordrecht
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Contents
CONTENTS v
ABBREVIATIONS ix
ACKNOWLEDGEMENTS xi
PREFACE xiii
CHAPTER 1 – INTRODUCTION 1
1.1 MOTIVATION AND CONTEXT 1
1.2 GOALS 4
CHAPTER 2 – GENERAL DESIGN CONSIDERATIONS IN PIPELINED
A/D CONVERTERS 7
2.1 INTRODUCTION 7
2.2 PERFORMANCE PARAMETERS IN NYQUIST A/D CONVERTERS 7
2.2.1 STATIC PARAMETERS 9
2.2.1.1Offset, full-scale and gain errors 9
2.2.1.2Integral Non-Linearity and Differential Non-linearity errors 10
2.2.2 DYNAMIC PARAMETERS 11
2.2.2.1Signal-to-Noise Ratio 12
2.2.2.2TotalHarmonic Distortion 12
2.2.2.3Spurious Free Dynamic Range 13
2.2.2.4Signal-to-Noise plus Distortion Ratio 13
vi
2.2.2.5 Effective Number of Bits and Effective Resolution Bandwidth 13
2.2.2.6 Dynamic DNL and INL 14
2.3 MAIN NON-IDEALITIES IN PIPELINED A/D CONVERTERS 15
2.3.1 NON-IDEALITIES IN THE FLASH QUANTIZERS 18
2.3.2 RESIDUE AMPLIFICATION GAIN-ERROR IN THE MDACS 20
2.3.3 NON-LINEARITY ERRORS IN THE MDACS 21
2.3.4 THERMAL NOISE 22
2.3.5 JITTER NOISE 22
2.3.6 ALIASING 23
2.4 OVERVIEW AND COMPARISON OF PUBLISHED WORKS IN
PIPELINED A/D CONVERTERS 24
2.4.1 FIGURES-OF-MERIT 24
2.4.2 DISCUSSION 26
2.5 CONCLUSIONS 28
CHAPTER 3 – ANALOGUE CODE-BY-CODE SELF-CALIBRATION
TECHNIQUE 33
3.1 INTRODUCTION 33
3.2 SYSTEM ARCHITECTURE 34
3.2.1 BLOCK DIAGRAM 34
3.2.2 MDAC AND ERRORS TO BE CALIBRATED 35
3.3 THE SELF-CALIBRATION TECHNIQUE 37
3.3.1 CALIBRATION OF THE GAIN ERROR OF THE MDAC 37
3.3.2 CALIBRATION OF THE NON-LINEARITY ERRORS OF THE
MDAC 38
3.3.3 CONVERSION MODE 40
3.3.4 CALIBRATION OF THE FULL-SCALE AND OFFSET ERRORS
OF THE REFDAC 41
3.4 INTEGRATED MDAC PROTOTYPE AND MEASURED RESULTS 42
3.5 BEHAVIOURAL SYSTEM SIMULATIONS OF A HIGH-RESOLUTION
PIPELINED ADC 47
3.6 CONCLUSIONS 52
vii
CHAPTER 4 – SYSTEMATIC DESIGN METHODOLOGY FOR
OPTIMISATION OF HIGH-SPEED SELF-CALIBRATED PIPELINED
ADCS 55
4.1 INTRODUCTION 55
4.2 ARCHITECTURE DESCRIPTION 56
4.3 DESIGN CONSIDERATIONS 59
4.3.1 THERMAL NOISE CONSTRAINTS 59
4.3.2 OTA REQUIREMENTS IN THE MDAC 62
4.3.3 SPECIFICATIONS FOR THE ON-RESISTANCE OF THE
SWITCHES IN THE MDAC 63
4.3.4 SPECIFICATIONS FOR THE FLASH QUANTIZER 64
4.3.5 SELF-CALIBRATION REQUIREMENTS 65
4.4 POWER AND AREA ESTIMATION 66
4.4.1 POWER ESTIMATION 66
4.4.2 AREA ESTIMATION 68
4.5 OPTIMISATION 69
4.5.1 METHODOLOGY 69
4.5.2 DISTRIBUTION OF THE NOISE CONTRIBUTIONS IN THE
PIPELINE 71
4.6 DESIGN EXAMPLE 72
4.7 CONCLUSIONS 77
CHAPTER 5 – DESIGN OF A 14-BIT 5 MS/S CMOS PIPELINED A/D
CONVERTER 83
5.1 INTRODUCTION 83
5.2 SPECIFICATIONS, ARCHITECTURE DEFINITION AND
BACKGROUND SELF-CALIBRATION OF THE OVERALL CONVERSION
SYSTEM 84
5.2.1 SPECIFICATIONS 84
5.2.2 ARCHITECTURE 84
5.2.3 ON-THE-FLY BACKGROUND CALIBRATION CONCEPT 85
5.3 DESIGN OF THE BASIC BUILDING BLOCKS 87
5.3.1 DESIGN OF THE 8-BIT 5MS/S BACKEND ADC 87
viii
5.3.1.1 The 1.5-bit MDAC 88
5.3.1.2 The 1.5-bit Flash Quantizer 92
5.3.2 DESIGN OF THE 7-BIT 5MS/S FRONT-END ADC 95
5.3.2.1 The Front-end Sample-and-Hold 95
5.3.2.2 The 4-bit MDAC 99
5.3.2.3 The 4-bit Flash Quantizer 103
5.3.2.4 The REFDAC 107
5.3.2.5 The 12-bit CALDAC 110
5.3.2.6 The High Accuracy Comparator 115
5.3.2.7 The Reference Buffering Circuitry 117
5.3.2.8 Biasing Circuitry 120
5.3.2.9 The Non-Overlapping Clock generators 120
5.3.3 DESIGN OF THE DIGITAL BUILDING BLOCKS 122
5.3.3.1 The Digital Correction Logic 122
5.3.3.2 The Controller and the Memories 122
5.3.3.3 Testing Modes 123
5.4 DESIGN OF THE OVERALL SYSTEM AND FUNCTIONAL
SIMULATIONS 123
5.5 CONCLUSIONS 125
CHAPTER 6 – INTEGRATED PROTOTYPES OF PIPELINED ADCS
AND MEASURED RESULTS 129
6.1 INTRODUCTION 129
6.2 INTEGRATED PROTOTYPE OF AN 8-BIT 5MS/S PIPELINED ADC
WITH MINIMUM BIT-PER-STAGE ARCHITECTURE 130
6.3 INTEGRATED PROTOTYPE OF A 14-BIT 5MS/S BACKGROUND
SELF-CALIBRATED PIPELINED ADC WITH A POWER/AREA
OPTIMISED ARCHITECTURE 133
6.3.1 LAYOUT CONSIDERATIONS 135
6.3.2 MEASUREMENT SETUP 137
6.3.3 MEASURED RESULTS 139
6.4 CONCLUSIONS 143
CHAPTER 7 – CONCLUSIONS 147
APPENDIXES 149
Abbreviations
AC Alternating Current
A/D Analogue-to-Digital
ADC Analogue-to-Digital Converter
ADSL Asymmetrical Digital Subscriber Line
AFE Analogue Front-end
BiCMOS Bipolar Complementary Metal Oxide Semiconductor
CALDAC Calibrating Digital-to-Analogue Converter
CMOS Complementary Metal Oxide Semiconductor
D/A Digital-to-Analogue
DAC Digital-to-Analogue Converter
DC Direct Current
DCL Digital Correction Logic
DLL Delay-Locked Loop
DMT Discrete Multi-Tone
DNL Differential Non-Linearity
ENOB Effective Number of Bits
EPROM Erasable Programmable Read Only Memory
ERB Effective Resolution Bandwidth
FFT Fast Fourier Transform
FM Figure of Merit
Figure-Of-Merit 1
Figure-Of-Merit 2
FPGA Field-Programmable Gate Array
GBW Gain-Bandwidth Product
HAC High-Accuracy Comparator
HDTV High-Definition Television
IC Integrated Circuit
ISDN Integrated-Services Digital Networks
INL Integral Non-Linearity
LSB Least Significant Bit
x
MDAC Multiplying Digital-to-Analogue Converter
MSB Most Significant Bit
NMOS N-channel MOSFET
NS Number of Stages
OPAMP Operational Amplifier
OTA Operational Transconductance Amplifier
PMOS P-channel MOSFET
POTS Plain Old Telephone Service
QAM Quadrature Amplitude Modulation
RAM Random Access Memory
REFDAC Reference Digital-to-Analogue Converter
SAR Successive-Approximation Register
SFDR Spurious Free Dynamic Range
SMD Surface-Mount Devices
SNR Signal-to-Noise Ratio
SNDR Signal-to-Noise-plus-Distortion Ratio
SR Slew Rate
S&H Sample-and-Hold
VHDL VHSIC Hardware Description Language
VHSIC Very High-Speed Integrated Circuit
VLSI Very Large Scale of Integration