System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search

28 Pages·1996·0.59 MB·English

DesignAutomationforEmbeddedSystems,2,5–32(1996)
(cid:176)c 1996KluwerAcademicPublishers,Boston.ManufacturedinTheNetherlands.
System Level Hardware/Software Partitioning
Based on Simulated Annealing and Tabu Search
PETRUELES [email protected];[email protected]
DepartmentofComputerandInformationScience,Linko¨pingUniversity,S-58183Linko¨ping,Sweden
and
ComputerScienceandEngineeringDepartment,TechnicalUniversityTimisoara,Bv.V.ParvanNr.2,
RO-1900Timisoara,Romania
ZEBOPENG [email protected]
DepartmentofComputerandInformationScience,Linko¨pingUniversity,S-58183Linko¨ping,Sweden
KRZYSZTOFKUCHCINSKI [email protected]
DepartmentofComputerandInformationScience,Linko¨pingUniversity,S-58183Linko¨ping,Sweden
ALEXADOBOLI [email protected]
ComputerScienceandEngineeringDepartment,TechnicalUniversityTimisoara,Bv.V.ParvanNr.2,
RO-1900Timisoara,Romania
ReceivedFebruary6,1996;RevisedJune10,1996
Abstract. Thispaperpresentstwoheuristicsforautomatichardware/softwarepartitioningofsystemlevelspec-
ifications. Partitioningisperformedatthegranularityofblocks, loops, subprograms, andprocesseswiththe
objectiveofperformanceoptimizationwithalimitedhardwareandsoftwarecost. Wedefinethemetricvalues
forpartitioninganddevelopacostfunctionthatguidespartitioningtowardsthedesiredobjective. Weconsider
minimizationofcommunicationcostandimprovementoftheoverallparallelismasessentialcriteriaduringpar-
titioning. Twoheuristicsforhardware/softwarepartitioning, formulatedasagraphpartitioningproblem, are
presented: onebasedonsimulatedannealingandtheotherontabusearch. Resultsofextensiveexperiments,
includingreal-lifeexamples,showtheclearsuperiorityofthetabusearchbasedalgorithm.
Keywords:Hardware/softwarepartitioning,co-synthesis,iterativeimprovementheuristics,simulatedannealing,
tabusearch.
1. Introduction
Newtoolswhichextenddesignautomationtosystemlevelhavetosupporttheintegrated
designofboththehardwareandsoftwarecomponentsofanembeddedsystem[39],[18].
The input specification accepted by such design tools describes the functionality of the
systemtogetherwithsomedesignconstraintsandistypicallygivenasasetofinteracting
processes. Many embedded systems have strong requirements concerning the expected
performance. Satisfaction of these performance constraints can frequently be achieved
onlybyhardwareimplementationofsomecomponentsofthespecifiedsystem. Thiscanbe
realizedbyusingdedicatedASICs(applicationspecificintegratedcircuits)orFPGAs(field-
programmablegatearrays)aspartoftheimplementationarchitecture. Anothersolutionin
6 ELES,PENG,KUCHCINSKI,ANDDOBOLI
ordertomeetdesignrequirementsistodevelopanASIP(applicationspecificinstruction-
setprocessor)withacarefullyselectedinstruction-setandarchitecture,whichproducesthe
requiredperformanceforthegivenapplication[20].
Theterm“hardware/softwareco-design”isusedtodaytodenotethecooperativedevel-
opmentprocessofboththehardwareandthesoftwarecomponentsofasystem. According
to traditional methodologies the hardware and software parts of an application are sepa-
rately developed and their final integration is based on ad hoc methods, which increases
time-to-marketandcost,andveryoftendecreasesqualityandreliabilityoftheproduct.
Research in hardware/software co-design aims to develop methodologies and tools for
asystematicandconcurrentdevelopmentofthehardwareandsoftwarecomponents,pro-
vidinginteractionandexplorationoftrade-offsalongthewholedesignprocess. Thus,the
actualareaofco-designcoversseveralaspectsofthedesignprocess: systemspecification
and modeling, co-simulation of heterogeneous systems, partitioning, system verification,
compilation,hardwareandsoftwaresynthesis,interfacegeneration,performanceandcost
estimation,andoptimization. Thereadercanfindoverviewsconcerningthemaintrendsof
thisverydynamicareain[7],[9],[11],[12],[18],[31],[39].
Thispaperconcentratesontheselectionoftheappropriatepartofthesystemforhardware
and software implementation respectively, known as the hardware/software partitioning
problem. Hardware/softwarepartitioningisoneofthemainchallengesduringthedesignof
embeddedapplications,asithasacrucialimpactbothonthecostandtheoverallperformance
oftheresultedproduct.
For small systems with a very well understood structure and functionality, the number
of realistic alternatives of hardware/software partitioning is small. Thus, assignment of
functionality to the hardware and software domains can be performed using an ad hoc
approach based on the designer’s experience and intuition [6]. The main problems to
be solved are in this case hardware and software synthesis, co-simulation, and interface
generation.
Ifthespecifiedsystemislarge,withacomplexfunctionalityresultingfromahighnum-
ber of interacting components, the number of partitioning alternatives is extremely large
andtheirimpactoncostandperformancecannotbeestimatedwithoutsupportofadesign
tool[18]. Differentpartitioningschemescanbeinvestigatedwithsupportofhighperfor-
manceheuristicsbasedonadequatecostfunctionsandestimations. Suchacomputeraided
partitioningtechniqueisacrucialcomponentofanyco-designenvironment[8].
Severalapproacheshavebeenpresentedforthepartitioningofhardware/softwaresystems.
They differ in the initial specification, the level of granularity at which partitioning is
performed, the degree of automation of the partitioning process, the cost function, and
the partitioning algorithm. In [23], [17], [3], [34], [38], [1], [33] automatic partitioning
isperformed,whiletheapproachespresentedin[2],[14],[27],[10]arebasedonmanual
partitioning. Partitioningatafinegrainedlevelisperformedin[23],[17],[3]. In[2],[28],
[38],[1],[41]partitioningisperformedatacoarsergranularity.
Iterativeimprovementalgorithmsbasedonneighborhoodsearcharewidelyusedforhard-
ware/softwarepartitioning. Inordertoavoidbeingtrappedinalocalminimumheuristics
areimplementedwhichareveryoftenbasedonsimulatedannealing[17],[35],[1]. This
ismainlyduetothefactthatsimulatedannealingalgorithmscanbequicklyimplemented
SYSTEMLEVELHARDWARE/SOFTWAREPARTITIONING 7
andarewidelyapplicabletomanydifferentproblems. Atthesametimealimitationofthis
methodistherelativelylongexecutiontimeandthelargeamountofexperimentsneeded
totunethealgorithm.
In [38] a hardware/software partitioning algorithm is proposed which combines a hill
climbingheuristicwithbinarysearchalgorithm. Itminimizeshardwarecostwhilesatisfying
certainperformanceconstraints. Thisdiffersfromourapproachwhichtriestomaximize
performanceundergivenhardwareandsoftwarecostconstraint. Thepartitioningstrategy
presentedin[28]combinesagreedyalgorithmwithanouterloopalgorithmwhichtakes
into account global measures. Similar to [34] and [41] this approach is based on exact
knowledgeofexecutiontimesforeachtaskimplementedinhardwareorsoftwareandof
all communication times. These assumptions impose hard restrictions on the features of
thesystemspecificationsacceptedasinput. Inourapproachwedonotnecessarilyimpose
such limitations, which broadens the range of applications. Integer Linear Programming
formulationsofthehardware/softwarepartitioningproblemareproposedin[5],[33].
Theapproachdescribedin[1]issimilartooursinthesensethatperformancehastobe
maximized(intermsofexecutiontime)choosingtheappropriateimplementationtechnol-
ogyforasetoftasks,undercertaincostassumptions. Estimationsusedduringoptimization,
which is based on simulated annealing, are valid only under the assumption of a single,
staticallyscheduledprocessasthesoftwarecomponent.
Our design environment accepts as input a system level, implementation independent
specification of an application. The synthesized system has to produce maximal perfor-
mance (in terms of execution speed) using a given amount of hardware and software re-
sources. Automaticpartitioningatacoarsegrainlevel(process,subprogram,loop,block)
isourapproachtoachievethisgoalduringsystemleveldesign. Asperformanceandcostes-
timationsatthislevelareinherentlyapproximate,ourdesignprocessallowsre-partitioning
inlaterstepswhichisperformedbymovingfunctionalityfromonedomaintotheother,if
needed[37].
Ourpartitioningstrategyisbasedonmetricvaluesderivedfromprofiling(simulation),
staticanalysisofthespecification,andcostestimations. Weconsiderthatminimizationof
communicationcostbetweenthesoftwareandthehardwarepartitionandimprovementof
the overall parallelism are of outstanding importance during partitioning at system level.
Relatively low performances reported in [34] and [14] are, for example, caused by high
communication costs between the hardware and software domains, which have not been
minimized.
Wehaveimplementedfirstasimulatedannealingbasedalgorithmforhardware/software
partitioning. We show that important reduction of execution time can be achieved by
considering even small application specific improvements at algorithm design. We then
implementedourpartitioningalgorithmusingthetabusearchmethod. Basedonextensive
experiments we show that tabu search results in much better execution speed and clearly
outperformssimulatedannealing.
The paper is divided into 5 sections. Section 2 introduces the structure of the hard-
ware/software co-synthesis environment and discusses some assumptions concerning the
inputspecificationandthetargetarchitecture. Partitioningsteps,themetricvalues,andthe
proposed cost function are presented in section 3. In section 4 we discuss our simulated
8 ELES,PENG,KUCHCINSKI,ANDDOBOLI
Figure1.Overviewoftheco-synthesisenvironment.
annealing and tabu search based partitioning heuristics, evaluate their performance and
compare them based on results of extensive experiments. Finally, section 5 presents the
conclusions.
2. TheCo-SynthesisEnvironment
Anoverviewofthestructureofourhardware/softwareco-synthesisenvironmentisdepicted
in Figure 1. The input specification describes system functionality without prescribing
the hardware/software boundary or implementation details. A basic assumption is that
thisspecificationisformulatedasasetofprocessesinteractingviamessagestransmitted
throughcommunicationchannels. Wealsoassumethatthisspecificationisexecutableand
thatprofilinginformationcanbegenerated.
ThecurrentimplementationacceptsinputdesignsspecifiedinanextendedVHDLwhich
includes a synchronous message passing mechanism for process communication. The
interprocesssynchronizationandcommunicationmechanismprovidedbystandardVHDL
[25] is at a low level and its semantics is defined in terms of simulation. This makes
reasoningaboutprocessesandtheirinteractionaswellassynthesisextremelydifficultand
inefficient. In[15]wepresentamodelforsystem-levelspecificationofinteractingVHDL
processesanddescribethesynthesisstrategywehavedevelopedforit. Accordingtothe
model,processesarethebasicmodulesofthedesign,andtheyinteractusingasynchronous
SYSTEMLEVELHARDWARE/SOFTWAREPARTITIONING 9
message passing mechanism with predefined send/receive commands. Communication
channelsarerepresentedbyVHDLsignals. Usingthismodel, communicationinterfaces
between processes can be easily established or modified during automatic partitioning,
when new processes are created or functionality is moved from one process to another.
Designs formulated according to this model are translated by a simple preprocessor into
standardVHDLmodelsforsimulationpurpose[15].
In the context of our co-synthesis environment, a VHDL description corresponding to
our system-level specification model can be simulated, partitioned, and synthesized into
hardwareandsoftwarecomponents.
Whenthefinalpartitioningisdone, thehardwareimplementationissynthesizedbythe
CAMADhigh-levelsynthesis(HLS)system[36]. Thehardwareimplementationisconsid-
eredasaspecializedcoprocessorwhichinteractswiththesoftwaregeneratedbyacompiler
[21]. Wehavemadethefollowingassumptionsconcerningthetargetarchitecture:
1. There is a single programmable component (microprocessor) executing the software
processes(witharun-timesystemperformingdynamicscheduling);
2. The microprocessor and the hardware coprocessor are working in parallel (the archi-
tecturedoesnotenforceamutualexclusionbetweenthesoftwareandhardware);
3. Reducingtheamountofcommunicationbetweenthemicroprocessor(softwareparti-
tion) and the hardware coprocessor (hardware partition) improves the overall perfor-
manceoftheapplication.
Thispaperconcentratesonthefront-endoftheco-synthesisenvironment,whichperforms
extractionofperformancecriticalregionsandhardware/softwarepartitioning.
3. PartitioningStepsandtheCostFunction
Partitioning starts from an initial system specification described as a set of processes in-
teractingthroughcommunicationchannels. Thisspecificationisfurtherdecomposedinto
unitsofsmallergranularity. Thepartitioningalgorithmgeneratesasoutputamodelconsist-
ingoftwosetsofinteractingprocesses: theprocessesinonesetaremarkedascandidates
forhardwareimplementation,whiletheprocessesintheothersetaremarkedassoftware
implementationcandidates. Themaingoalofpartitioningistomaximizeperformancein
termsofexecutionspeed. Inordertoachievethiswedistributefunctionalitybetweenthe
softwareandthehardwarepartitionstakingintoaccountcommunicationcostandoverall
parallelism of the synthesized system. Thus, the following three objectives have to be
considered:
1. To identify basic regions (processes, subprograms, loops, and blocks of statements)
which are responsible for most of the execution time in order to be assigned to the
hardwarepartition;
2. Tominimizecommunicationbetweenthehardwareandsoftwaredomains;
3. Toincreaseparallelismwithintheresultedsystematthefollowingthreelevels:
10 ELES,PENG,KUCHCINSKI,ANDDOBOLI
– internalparallelismofeachhardwareprocess(duringhigh-levelsynthesis,opera-
tionsarescheduledtobeexecutedinparallelbytheavailablefunctionalunits);
– parallelismbetweenprocessesassignedtothehardwarepartition;
– parallelism between the hardware coprocessor and the microprocessor executing
thesoftwareprocesses.
Thepartitioningalgorithmtakesintoaccountsimulationstatistics,informationfromstatic
analysis of the source specification, and cost estimations. At the same time, all major
decisions taken by the design tool can be influenced through user interaction. Statistics
data are collected from simulation of an internal representation generated by a front-end
compiler,loadingthesystemwithsetsoftypicalinputstimuli. Twotypesofstatisticsare
usedbythepartitioningalgorithm:
1. Computation load (CL) of a basic region is a quantitative measure of the total com-
putation executed by that region, considering all its activations during the simulation
process. It is expressed as the total number of operations (at the level of internal
representation) executed inside that region, where each operation is weighted with a
coefficientdependingonitsrelativecomplexity:
X
CL D N act £` IN act isthenumberofactivationsof
i j opj j
opj2BRi
operationop belongingtothebasicregion BR I` istheweight
j i opj
associatedtothatoperation.
Therelativecomputationload(RCL)ofablockofstatements,loop,orasubprogram
isthecomputationloadoftherespectivebasicregiondividedbythecomputationload
oftheprocesstheregionbelongsto. Therelativecomputationloadofaprocessisthe
computationloadofthatprocessdividedbythetotalcomputationloadofthesystem.
2. Communicationintensity(CI)onachannelconnectingtwoprocessesisexpressedas
thetotalnumberofsendoperationsexecutedontherespectivechannel.
3.1. ThePartitioningSteps
Hardware/softwarepartitioningisperformedinfoursteps,whichareshowninFigure2:
1. Extractionofblocksofstatements,loops,andsubprograms: Duringthefirstpartitioning
stepprocessesareexaminedindividuallytoidentifyperformancecriticalregionsthat
are responsible for most of the execution time spent inside a process (regions with
a large CL). Candidate regions are typically loops and subprograms, but can also be
blocksofstatementswithahighCL.Thedesignerguidesidentificationandextraction
oftheregionsanddecidesimplicitlyonthegranularityoffurtherpartitioningstepsin
twoways:
a. Byidentifyingacertainregiontobeextracted(regardlessofitsCL)andassigning
ittothehardwareorsoftwarepartition(seealsosection3.3.). This,forinstance,
SYSTEMLEVELHARDWARE/SOFTWAREPARTITIONING 11
Figure2.Thepartitioningsteps.
canbethecaseforsomestatementsequenceonwhichahardtimeconstrainthas
beenimposedwhichcanbesatisfiedonlybyhardwareimplementation.
b. Byimposingtwoboundaryvalues:
– a threshold X on the RCL of processes that are examined for basic region
extraction;
– a threshold Y on the RCL of a block, loop, or subprogram to be considered
forbasicregionextraction.
ThesearchforcandidateregionsinprocesseswithRCLgreaterthan X isperformed
bottom-up, starting from the inner blocks, loops, and the subprograms that are not
containing other basic regions. When a region has been identified for extraction, a
new process is built to have the functionality of the original block, loop, or subpro-
gram and communication channels are established to the parent process. In [16] we
showhowextractionofcriticalregionsandprocessgenerationissolvedinourcurrent
implementation.
2. Process graph generation: During the second step an internal structure, called the
processgraph,isgenerated. Thisstepwillbediscussedinsection3.2.
12 ELES,PENG,KUCHCINSKI,ANDDOBOLI
3. Partitioning of the process graph: We formulate hardware/software partitioning as a
graph partitioning problem performed on the process graph. In section 4 we present
twoalgorithmswhichhavebeenimplementedforgraphpartitioningandcomparetheir
performance.
4. Process merging: During the first step one or several child processes are possibly
extractedfromaparentprocess. If,asresultofstep3,someofthechildprocessesare
assigned to the same partition with their parent process, they are, optionally, merged
backtogether.
3.2. TheProcessGraph
The input to the second partitioning step is a set of interacting processes. Some of them
are originally specified by the designer, others are generated during extraction of basic
regions. Statisticsconcerningcomputationloadofthegeneratedprocessesandcommuni-
cationintensityonthenewlycreatedchannelsareautomaticallyrecomputedduringthefirst
partitioningstep. Thedatastructureonwhichhardware/softwarepartitioningisperformed
istheprocessgraph. Eachnodeinthisgraphcorrespondstoaprocessandanedgeconnects
twonodesifandonlyifthereexistsatleastonedirectcommunicationchannelbetweenthe
correspondingprocesses.
Thegraphpartitioningalgorithmtakesintoaccountweightsassociatedtoeachnodeand
edge. Node weights reflect the degree of suitability for hardware implementation of the
correspondingprocess. Edgeweightsmeasurecommunicationandmutualsynchronization
between processes. The weights capture simulation statistics (CL, RCL, and CI) and
information extracted from static analysis of the system specification or of the internal
representation resulted after its compilation. The following data extracted from static
analysisarecaptured:
Nr op : totalnumberofoperationsinthedataflowgraphofprocessi;
i
Nr kind op : numberofdifferentoperationsinprocessi;
i
L path : lengthofthecriticalpath(intermsofdatadependency)throughprocessi.
i
Theweightassignedtoprocessnodei,hastwocomponents. Thefirstone,W1N,isequal
i
totheCLoftherespectiveprocess. Thesecondoneiscalculatedbythefollowingformula:
W2N D MCL £KCL CMU £KU CMP £KP ¡MSO £KSOI
i i i i i
where:
KCL isequaltotheRCLofprocessi,andthusisameasureofthecomputationload;
i
Nr op
KU D i ; KU isameasureoftheuniformityofoperationsinprocessi;
i Nr kind op i
i
Nr op
KP D i ; KP isameasureofthepotentialparallelisminsideprocessi;
i L path i
i
SYSTEMLEVELHARDWARE/SOFTWAREPARTITIONING 13
P
w
KSO D opj2SPi opj; KSO capturesthesuitabilityofoperationsofprocessi forsoft-
i nr op i
i
ware implementation. SP is the set of such operations (floating point computation, file
i
access,pointeroperations,recursivesubprogramcall,etc.) inprocessiandw isaweight
opj
associated to operation op , measuring the degree to which the operation has to be im-
j
plemented in software; a large weight associated to such an operation dictates software
implementationforthegivenprocess,regardlessofothercriteria.
Therelationbetweentheabove-namedcoefficients KCL, KU, KP, KSO isregulatedby
fourdifferentweight-multipliers: MCL, MU, MP,and MSO,controlledbythedesigner.
Both components of the weight assigned to an edge connecting nodes i and j depend
on the amount of communication between processes i and j. The first one is a measure
ofthetotaldataquantitytransferredbetweenthetwoprocesses. Thesecondonedoesnot
considerthenumberofbitstransferredbutonlythedegreeofsynchronizationbetweenthe
processes,expressedinthetotalnumberofmutualinteractionstheyareinvolvedin:
X X
W1E D wd £CI I W2E D CI I
ij ck ck ij ck
ck2Chij ck2Chij
whereCh isthesetofchannelsusedforcommunicationbetweenprocessesi and j;wd
ij ck
isthewidth(numberoftransportedbits)ofchannelc inbits;CI isthecommunication
k ck
intensityonchannelc .
k
3.3. CostFunctionandConstraints
Aftergenerationoftheprocessgraphhardware/softwarepartitioningcanbeperformedas
agraphpartitioningtask. Theweightsassociatedtothenodesandedgesmustbecombined
intoacostfunctionwhichguidespartitioningtowardsthedesiredobjectiveandhastobe
easilyupdatedafterpassingfromacurrentsolutiontoanewone.
Ourhardware/softwarepartitioningheuristicsareguidedbythefollowingcostfunction
whichistobeminimized:
P
P
W2E
X 9.ij/ ij
C.Hw;Sw/ D Q1£ W1E CQ2£ .i/2Hw W1iN
ij N
.ij/2ˆcutP P H !
W2N W2N
¡Q3£ .i/2Hw i ¡ .i/2Sw i I
N N
H S
whereHwandSwaresetsrepresentingthehardwareandthesoftwarepartitionrespectively;
N and N arethecardinalityofthetwosets; cut isthesetofedgesconnectingthetwo
H S
partitions;.ij/istheedgeconnectingnodesi and j;and.i/representsnodei.
Minimization of this function produces an implementation which corresponds to the
partitioningobjectivesstatedatthebeginningofsection3. Thepartitioningobjectivesare
capturedbythethreetermsofthecostfunction:
– Thefirsttermrepresentsthetotalamountofcommunicationbetweenthehardwareand
thesoftwarepartition. Decreasingthiscomponentofthecostfunctionreducesthetotal
14 ELES,PENG,KUCHCINSKI,ANDDOBOLI
amount of communication between partitions, which is a primary design goal. As a
secondeffectitalsoimprovesparallelismbetweenprocessesinthehardwarepartition
and those implemented in software. This is an implicit result of reduced interaction
betweenthetwopartitions.
– Thesecondtermstimulatesplacementintohardwareofprocesseswhichhaveareduced
amountofinteractionwiththerestofthesystemrelativetotheircomputationloadand,
thus,areactivemostofthetime. Thisstrategyimprovesparallelismbetweenprocesses
inside the hardware partition whePre physical resources are allocated for real parallel
execution. Foragivenprocessi,. W2E/=W1N isthetotalamountofinteraction
9.ij/ ij i
theprocessisinvolvedin,relativetoitscomputationload. Thewholetermrepresents
theaverageofthisvalueoverthenodesinthehardwarepartition.
– Thethirdterminthecostfunctionpushesprocesseswithahighnodeweightintothe
hardwarepartitionandthosewithalownodeweightintothesoftwareone,byincreasing
thedifferencebetweentheaverageweightofnodesinthetwopartitions. Thisisabasic
objectiveofpartitioningasitplacestimecriticalregionsintohardwareandalsoexploits
thepotentialofhardwaretoimplementinternalparallelismofprocesses.
The criteria combined in the cost function are not orthogonal, and sometimes compete
with each other. Moving a high node weight process into hardware, for instance, can
produceanincreaseinthecommunicationbetweenpartitions. Thiscompetitionbetween
partitioningobjectivesiscontrolledbythedesignerthroughthecostmultipliers Q1, Q2,
and Q3whichregulatetherelativeinfluenceofthedifferentmetrics.
Minimizationofthecostfunctionhastobeperformedinthecontextofcertainconstraints.
Thus, our heuristics have to produce a partitioning with a minimum for C.Hw;Sw/, so
thatthetotalhardwareandsoftwarecostiswithinsomeuserspecifiedlimits:
X X
H cost •MaxHI S cost •MaxS:
i i
.i/2Hw .i/2Sw
Apreassignmentofprocesseswhicharedefinitivelyassignedtooneofthepartitionscan
beperformedoptionallybythedesigner. Oftenthispreassignmentisformulatedinterms
oftheweights: nodeswithaweightsmallerthanagivenlimithavetogointosoftwareand
thosewithaweightgreaterthanacertainlimitshouldbeassignedtohardware:
W2N ‚ Lim1).i/2 HwI W2N • Lim2).i/2 Sw:
i i
Costestimationhastobeperformedbeforegraphpartitioning,forboththehardwareand
software implementation alternatives of the processes. In the current implementation of
our environment, the CAMAD high level synthesis system [36] produces hardware cost
estimationsintermsofdesignarea. Softwarecost,intermsofmemorysize,isestimated
foreachprocessthroughcompilationbyourVHDLtoCcompiler[21].
4. PartitioningAlgorithmsandExperimentalResults
As a final step of the hardware/software partitioning process the weighted graph is to be
partitionedintotwosubgraphs. Thepartitionscontainingnodesassignedtohardwareand