System level ESD co-design

429 Pages·2015·27.906 MB·English

by  Duvvury, Charvaka, Gossner, Harald

SYSTEM LEVEL ESD
CO-DESIGN
SYSTEM LEVEL ESD
CO-DESIGN
Editedby
CharvakaDuvvury
IndependentESDIndustryConsultant,Texas,USA
Harald Gossner
IntelMobileCommunications,Munich,Germany
Thiseditionfirstpublished2015
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LibraryofCongressCataloging-in-PublicationData
Duvvury,Charvaka,1944-
SystemlevelESDco-design/CharvakaDuvvury,IndependentESDIndustryConsultant,Texas,USA,
HaraldGossner,IntelMobileCommunications,Munich,Germany.
pagescm
Includesbibliographicalreferencesandindex.
ISBN978-1-118-86190-5(hardback)
1.Shielding(Electricity)2.Electronicapparatusandappliances–Designandconstruction.3.Integrated
circuits–Designandconstruction.4.Integratedcircuits–Protection.5.Electrostatics.6.Staticeliminators.
I.Gossner,Harald.II.Title.
TK7867.8.D882015
537′.2–dc23
2015008307
AcataloguerecordforthisbookisavailablefromtheBritishLibrary.
Typesetin10/12ptTimesLTStdbyLaserwordsPrivateLimited,Chennai,India
1 2015
Contents
ListofContributors xiii
Preface xv
Acronyms xvii
AbouttheBook xxi
1 Introduction 1
CharvakaDuvvury
1.1 DefinitionofCo-Design 1
1.2 OverviewoftheBook 2
1.3 ChallengesofSystemLevelESDProtection 2
1.4 ImportanceofSystemLevelProtection 2
1.5 Industry-WidePerception 5
1.6 PurposeandMotivation 8
1.7 OrganizationandApproach 8
1.8 OutcomefortheReader 12
Acknowledgments 12
References 12
2 ComponentversusSystemLevelESD 14
CharvakaDuvvuryandHaraldGossner
2.1 ESDThreatintheRealWorld 14
2.1.1 ESDControl 14
2.1.2 ESDFailureTypes 15
2.1.3 ESDProtectionAreas 16
2.1.4 ESDStressModels 17
2.2 ComponentESDQualification 17
2.2.1 ComponentESDTests 17
2.2.2 ESDLevelsforICProduction 18
2.2.3 ImplicationsforSystemLevelESD 20
2.2.4 ESDTechnologyRoadmap 20
vi Contents
2.3 SystemLevelESDTests 21
2.3.1 IEC61000-4-2 22
2.4 ISO10605 29
2.5 IEC61000-4-5 31
2.5.1 SystemApplications 32
2.5.2 MisconceptionsandMiscorrelationofComponentand
SystemLevelTests 35
2.5.3 HardFailuresDuetoIECTesting 42
2.6 SoftFailuresDuetoIECTesting 42
Acknowledgments 43
References 43
3 SystemLevelTestingforESDSusceptibility 46
MichaelHopkins
3.1 Introduction 46
3.2 ObjectivesofSystemLevelTesting 47
3.3 CompliancetoESDStandards 47
3.3.1 LegalComplianceRequirements 47
3.3.2 CompliancetoIndustryRequirements 48
3.4 TestingforProductReliability 48
3.5 StandardsRequirementsforSystemLevelTesting 49
3.5.1 IEC61000-4-2 49
3.5.2 AutomotiveStandardsforESD 58
3.5.3 MedicalStandardsforESD 60
3.5.4 AvionicsStandardsforESD 61
3.5.5 MilitaryESDStandards 61
3.6 UsingtheIECSimulatorforDeviceTesting 62
3.7 CableDischarge(CDE)Testing 63
3.7.1 ShieldedCables 65
3.7.2 UnshieldedCables 65
3.7.3 ModifiedTransmissionLinePulsers(TLP)forCDETesting 66
3.8 EvaluationofTestResults 67
3.8.1 HardFailureEvaluation 67
3.8.2 SoftFailureEvaluation 67
3.9 TheQuickFixvsRootCauseDetermination 67
3.10 DeterminingRootCauseofSystemLevelESD 68
3.11 ReproducibilityofSystemLevelESDTests 70
Acknowledgments 72
References 72
4 PCB/ICCo-DesignConceptsforSEED 74
HaraldGossnerandCharvakaDuvvury
4.1 On-ChipSystemESDProtection 74
4.1.1 HBMandCDMvsIEC 74
Contents vii
4.1.2 TLPCharacterization 76
4.1.3 TLPCorrelationIssues 78
4.2 Off-ChipESDProtection 79
4.3 ConceptofPCB/ICCo-Design 82
4.3.1 On-ChipIECProtectionSolutions 84
4.4 IntroductiontoSystemEfficientESDDesign 84
4.4.1 DesignMethodsforSEED 90
4.4.2 BasicSimulationsusingSEED 91
4.4.3 USBDesignusingSEED 94
4.5 CharacterizationforHardFailures 97
4.6 SimulationofSystemLevelESDDischargePaths 98
4.6.1 SimulationApproach 98
4.6.2 Tools 101
4.6.3 ESDModelTypes 103
4.6.4 ExtractionofPCBPaths 104
4.6.5 ModelsofPCBDevices 104
4.6.6 CharacterizationofIOCells 106
4.6.7 PowerClampModels 112
4.6.8 ModelforStressWaveform 114
4.7 CharacterizationofSoftFailures 116
4.7.1 PurposeandBasicConcept 116
4.7.2 PinSpecificSoftFailureCharacterization 120
4.7.3 SoftFailuresRelatedtoSignalIntegrityProblems 123
4.8 SummaryofSEEDCharacterization 125
Acknowledgments 126
References 127
5 HardFailuresandPCBProtectionDevices 129
RobertAshton
5.1 Introduction 129
5.2 ESDDamagetoICs 129
5.3 ProtectionMethods 130
5.3.1 ClassificationofTVSDevices 133
5.4 CharacteristicsofProtectionDevices 134
5.4.1 CurrentLimitingDevices 134
5.4.2 TVSPropertiesinTheirOff-State 135
5.4.3 ProtectionPropertiesofTVSDevices 137
5.5 TypesofProtectionDevicesforESD 142
5.5.1 SiliconBasedTVSDevices 143
5.5.2 MetalOxideVaristors 154
5.5.3 PolymerVoltageSuppressors 155
5.5.4 GasDischargeTubes 156
5.5.5 SparkGapsonPCBs 158
5.5.6 ThyristorSurgeProtectionDevices 159
viii Contents
5.5.7 FerriteBeads 159
5.5.8 PassiveComponents 161
5.5.9 CommonModeFilters 162
5.6 PrimaryandSecondaryProtection 163
5.7 EvaluatingICPins 164
5.8 ChoosingESDProtectionDevices 164
5.8.1 CoordinationbetweenTVSDeviceandSensitiveNodes 165
5.9 Summary 167
References 167
6 SoftFailureMechanismsandPCBDesignMeasures 169
DavidPommerenkeandPratikMaheshwari
6.1 Introduction 169
6.2 AreHBM,CDM,MM,andLatch-UpResultsMeaningfulSoftFailures? 171
6.3 ClassificationofSoftFailureModes 173
6.3.1 In-Band/Out-of-BandwithRespecttoVoltage 174
6.3.2 In-Band/Out-of-BandwithRespecttoPulseWidth 175
6.3.3 LocalvsDistantErrors 176
6.3.4 Amplified/Non-amplifiedSoftFailures 176
6.4 OptimizedSystemLevelTesting 178
6.5 SoftFailureCharacterizationMethods 182
6.5.1 SusceptibilityScanning 183
6.5.2 CurrentSpreadingReconstruction 190
6.5.3 LocalInjection 191
6.5.4 Software-BasedMethodsforSoftFailureAnalysis 201
6.6 SoftFailureExamples 205
6.6.1 Example1:SoftFailureCausedbyFieldInjection
onaDUT(MiniPhotoFrame) 205
6.6.2 Example2:PLLDisturbanceMeasurement 207
6.6.3 Example3:DirectFieldCouplingontheUSBDataBus 212
6.6.4 Example4:DirectInjectionontheMIPIBusInterface 215
6.7 CountermeasureExamples 216
6.7.1 DivertCurrent 216
6.7.2 Filtering 217
6.7.3 Shielding 217
6.7.4 SecondaryESDAvoidance 218
6.7.5 ImprovedConnector-CableShieldConnection 218
6.7.6 EnclosuretoConnectorShieldJunction 218
6.7.7 Firmware 218
6.7.8 ReducingCrosstalk 219
6.7.9 ReduceESDCurrentbyResistance 220
6.7.10 AvoidESD 222
6.8 TheWayForward 223
Acknowledgment 230
References 231
Contents ix
7 ESDinMobileDevices 234
MattiUusimäki
7.1 Introduction 234
7.2 ESDEnergyPathinMobileDevice 234
7.3 ESDGenerationExamplesonaLargeScale 239
7.3.1 LargeMachinesGeneratingChargestoTheirIsolatedBodies 239
7.3.2 Tribo-ElectricSeries 240
7.3.3 ChargeGeneratedbyaPersonInsideaCar 240
7.3.4 TheChargeGeneratedtoMobileDevicebyAccident
inGroundedSystem 241
7.3.5 AlternativeDischargingPathsatConnectionMoment 244
7.3.6 ChargeBehavioratInsulatorSurface 244
7.3.7 ExampleofConsumerLevelChargeGenerationwithSimpleDevice 246
7.4 RelationbetweenElectrostaticDischargeImmunityTestandReal-World
DischargeWaveforms 248
7.5 LaboratoryTestMethods 248
7.6 FastESDandSlowESDConcepts 249
7.7 Fast-ESDandSlow-ESDinaMobileDevice 250
7.7.1 ExampleofGroundLevelBounceRelativetoanExternalModule 251
7.8 IsolatingaMobileDevice 252
7.8.1 Example1:MaterialThickness 252
7.8.2 Example2:SolidGlue 253
7.8.3 Example3:PositioningHolesinaRubberizedKeyMat 255
7.8.4 Example4:InducedElectricField 255
7.9 ShieldingaMobileDevice 257
7.10 OrientationEffectsonESDPath 259
7.10.1 ESDPathExample:PhoneFaceUponTable 259
7.10.2 ESDPathExample:PhoneFaceDownontheTable 263
7.11 ESDDesigninPractice 264
7.11.1 GroundingChallengesinPractice 264
7.12 PCBLayoutConsiderationsofMetalShielding“Cans” 267
7.12.1 ComponentsNeartheEdgeoftheShield 268
7.13 ESDProtectionforCableInterfaces 269
7.13.1 CablePlacementandCommonModeCurrentinaMobileDevice 270
7.13.2 LocalizingNoiseCurrentwithAlternateCablingPlacement 274
7.13.3 CableInterfaceProtectionComponents 275
7.14 CommonModeImpedanceConcernsforLayout 280
7.14.1 CommonModeImpedanceChallengesintheGroundingPaths 280
7.14.2 SignalswithSharedCommonModeImpedance 280
7.14.3 IsolatingSignalswithShieldGroundedtoInternalPCBLayers 282
7.14.4 SimulatedExampleofGroundImpedanceEffectonESD/EMI
FilterPerformance 283
7.14.5 ESDProtectiononStackedChips 283
7.14.6 LayoutConcernsaroundthePeripheryandPCBCutouts 285
7.15 ESDandSoftwareConsiderationsinMobileDevices 287
x Contents
7.15.1 RoleofSoftwareinEMCandESDDesign 287
7.15.2 SignalSensitivitytoESDExamples 288
7.15.3 DelayedEffectsonSoftwarefromESDEvents 290
7.16 SoftwareVersionsUtilizedinEarlyESDImmunityTesting 291
7.17 Conclusion 292
References 292
8 ESDforAutomotiveApplications 294
WolfgangReinprecht
8.1 IntroductionandHistoricalAspects 294
8.1.1 WhyDoAutomotiveComponentsRequireHighESDLevels? 294
8.1.2 FieldReturnRateofAutomotiveProductsduetoSystemLevel
ESDEvents 296
8.1.3 ESDRelatedFieldReturnsBecauseofIncompleteSpecificationor
MissingSystemProtection 297
8.2 AutomotiveComponents 299
8.2.1 CommunicationSystemsCAN,LIN,FlexRay 299
8.2.2 PowerSupplySystemsasDCDCConverter,Alternator,LDO 303
8.2.3 SensorsandSensorInterfaces 304
8.2.4 KeylessEntry/GowithComponentsExposedtoHuman
Touching/Handling 311
8.2.5 PowerSteering,DrivebyWire,Gearbox,HybridSystems,
Recuperation 313
8.2.6 LEDLights,Entertainment,Navigation,andAudio 313
8.3 DesignConstraints,OperatingVoltage,andOvervoltageTolerance 315
8.3.1 “NormalOvervoltageRange”:18Vinto5V/3V/1.8V 315
8.3.2 LoadDump 315
8.3.3 LossofGround,DualPolarity,andReversePolarity 317
8.3.4 EMCToleranceversusESDRobustness(FastTransients) 319
8.3.5 LeakageCurrentversusESDRobustness(Pre-PulseVoltage) 320
8.3.6 Latch-Up-FreeESDProtectionversusSnapbackDevices 321
8.4 On-BoardESDProtectionandInternalESDProtection 324
8.4.1 CharacterizationMethodstoGetRelevantDataforExternal
ESDDevices 324
8.4.2 ESDDesignWindowUsingExternalProtectionElements(TVS) 324
8.4.3 OptimizingOn-ChipESDProtectionstoMatchBoardLevel
Protection 324
8.4.4 On-BoardGroundShiftduetoSystemESDEvents 325
8.4.5 SecondaryEffectsasTransientDisturbancesto“Internal”Pins
(LateralCoupling) 326
8.4.6 PinPlacement,ExternalPassiveComponents,andBoard
LayoutConstraints 328
8.5 VerificationandQualification 329
8.5.1 SafeOperatingAreaChecktoVerifyOvervoltageTolerance 329
8.5.2 ESDDesignRuleChecktoVerifyESDConceptandConstraints 330
8.5.3 ESDTestsonChipLevelHBM/CDM 331
Contents xi
8.5.4 TLPCharacterizationofProducttoMeetSEED 331
8.5.5 SystemESDTestsonBoardLeveluptotheLevelofFailure 331
8.5.6 No-GosinTermsofESDDesign 332
8.6 Conclusion 332
References 333
9 FutureApplicationsofSEEDMethodology 334
HaraldGossnerandCharvakaDuvvury
9.1 RefinementofModels 334
9.2 LimitationsofSimulationandBeyond 337
9.2.1 RelationofSEEDtoSystemESDTests 337
9.2.2 OutlooktoaComprehensiveDesignVerification 341
9.3 AdvancestowardHigh-SpeedSystems 342
9.3.1 USBandHDMIChallenges 343
9.4 IssuesandChallengesofSystemProtection 345
9.4.1 USB2.0versusUSB3.0 345
9.4.2 USB2.0/3.0versusHDMI 346
9.4.3 AutomotiveTechnologies 346
9.4.4 ICPackageTechnologies 347
9.4.5 PCBTechnologies 347
9.4.6 OpticalInterfaces 348
9.4.7 PolymerMaterialApplications 348
9.5 BenefitsforNextGenerationSystems 349
9.5.1 HarmonizedApproachforComponenttoSystemProtection 349
9.5.2 IECSpecificationRequirements 350
9.5.3 CostofSystemProtection 351
Acknowledgments 351
References 351
10 Co-DesignTrade-Offs:BalancingRobustness,Performance,andCost 353
JeffreyC.Dunnihoo
10.1 Co-DesigningacrossFunctionalandCorporateBoundaries 353
10.1.1 Component(Factory)versusSystem(EndUser)ESDIssues 353
10.1.2 ProbabilitiesandUncertaintiesofSystemESDCosts 354
10.1.3 BoundedandCumulativeESDFailureProbability 355
10.1.4 ProductandOrganizationalResponsetoESDFailure 357
10.1.5 TheRealityofthe“RealCostofESD” 358
10.1.6 Co-DesigningaSolution 358
10.2 ESDGoalsandConstraints 359
10.2.1 TheCo-DesignGamut 359
10.2.2 ESDMarginRequirementBasedonUnknownProbabilities 360
10.2.3 ExtremeandAbusiveUsers 361
10.2.4 Ignoringthe“LongTail”Events 363
10.2.5 CapturingQuantitativeSystemFaultData 364
10.2.6 ESDSousveillance 364