Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

220 Pages·1996·6.699 MB·English

by  Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley (auth.)

SYNTHESIS OF POWER DISTRmUTION
TO MANAGE SIGNAL INTEGRITY IN
MIXED-SIGNAL ICs
SYNTHESIS OF POWER DISTRIBUTION
TO MANAGE SIGNAL INTEGRITY IN
MIXED-SIGNAL ICs
by
Balsha R. Stanisic
IBM, Rochester
Rob A. Rutenbar
Carnegie Mellon University
L. Richard Carley
Carnegie Mellon University
KLUWER ACADEMIC PUBLISHERS
Boston / Dordrecht / London
Distributors for North America:
Kluwer Academic Publishers
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Norwell, Massachusetts 02061 USA
Distributors for all other countries:
Kluwer Academic Publishers Group
Distribution Centre
Post Office Box 322
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Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
ISBN-13: 978-1-4612-8606-6 e-ISBN-13: 978-1-4613-1399-1
DOl: 10.1007/978-1-4613-1399-1
Copyright «:> 1996 by Kluwer Academic Publishers
Softcover reprint of the hardcover 1st edition 1996
All rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park,
Norwell, Massachusetts 02061
Printed on acid-free paper.
For Rastko, Lubica, Dick and Margie -BRS
For Martha, Peter and Colin -RAR
For Kathleen, Cassandra and Arianna -LRC
Contents
Contents ......................................................................... vii
L· t f F· ...
IS 0 Igures •••••••.••••••••••••••••••••.••••••••••••••••••••..•.•......•.• XIII
List of Tables ................................................................ xvii
Preface ........................................................................... xix
1 IntrOOuction ................................................................... 1
1.1 Focus .............................................................................................................. 1
1.2 Motivation ...................................................................................................... 1
1.3 Research Overview ........................................................................................ 3
1.4 Preview of Results ......................................................................................... .5
1.5 Book Organization ......................................................................................... 6
SYNTHESIS OF POWER DISTRIBUTION FOR MIXED-SIGNAL ICS
2 Power Distribution Noise
and Physical Design Methods .................................... 13
2.1 Analog Design Problem Characteristics ...................................................... 13
2.1.1 Scale ................................................................................................................. 14
2.1.2 Sensitivity ......................................................................................................... 14
2.2 Design Style Concerns ................................................................................. 15
2.2.1 Custom 2-D Macrocell ..................................................................................... 16
2.2.2 Row-Based Standard-Cell ................................................................................ 18
2.3 Analog Power Distribution Design Concerns .............................................. 19
2.3.1 Physical Design Concerns ............................................................................... 19
2.3.2 Electrical Concerns .......................................................................................... 21
2.4 Previous Research in Power Distribution Synthesis .................................... 25
2.4.1 Power Bus Topology Selection ......................................................................... 27
2.4.2 Power Bus Segment Width Sizing ..................................................................... 28
2.5 Critical Analysis ........................................................................................... 28
2.5.1 Meeting Design Style Concerns ....................................................................... 29
2.5.2 Meeting Physical Design Concerns ................................................................. 30
2.5.3 Meeting Electrical Concerns ............................................................................ 32
2.6 Concluding Remarks .................................................................................... 32
3 Physical Design and Optimization •.•.•.••••••••••••.••....•.. 39
3.1 New Optimization-based Strategy .............................................................. .40
3.2 Design Style Selection ................................................................................ .41
3.3 Power Bus Topology Selection and Sizing .................................................. 42
3.3.1 Formulation Objectives .................................................................................... 43
3.3.2 General Grid Formulation ............................................................................... 43
3.4 Power I/O Cell Assignment.. ....................................................................... .46
3.4.1 Formulation Objectives .................................................................................... 46
3.4.2 Configurable Cell Formulation ........................................................................ 46
3.5 Simultaneous Power Bus and I/O Cell Optimization .................................. .48
3.5.1 Design Variables .............................................................................................. 49
3.5.2 Objective .......................................................................................................... 49
3.5.3 Constraints ....................................................................................................... 51
3.5.4 Cost Surface Characterization ......................................................................... 52
3.5.5 DeSign Variable and Constraint Characterization ........................................... 55
3.5.6 Optimization Alternatives. ................................................................................ 57
viii
CONTENTS
3.6 Review of Simulated Annealing .................................................................. 59
3.7 Simulated Annealing Formulation ............................................................... 60
3.7.1 Representation .................................................................................................. 61
3.7.2 Move set ........................................................................................................... 66
3.7.3 Cost Function ................................................................................................... 73
3.7.4 Cooling Schedule ............................................................................................. 75
3.7.5 Invoked Evaluation Method ............................................................................. 77
3.8 Concluding Remarks .................................................................................... 78
4 DC, A C, and Transient Electrical Models
and Analysis ................................................................. 83
4.1 Electrical Formulation Objectives ................................................................ 84
4.1.1 Chip -> Chip & Package ................................................................................. 85
4.1.2 Geometry -> Geometry & Electricity .............................................................. 86
4.1.3 Simple DC -> DC, AC, & Transient ................................................................ 86
4.1.4 Predefined -> User-specified ........................................................................... 86
4.1.5 Efficient -> Accurate & Efficient. .................................................................... 87
4.2 Mapping Power Bus and 110 Cell Geometry
to Electricity ........................................................................................... '" ... 88
4.2.1 Power busses .................................................................................................... 88
4.2.2 Configurable UO Cells ..................................................................... ,. .............. 89
4.3 Modeling Macrocells .................................................................................... 91
4.3.1 Sources ............................................................................................................. 91
4.3.2 Power Distribution Coupling ........................................................................... 93
4.3.3 Example Models ............................................................................................... 95
4.4 Modeling Interconnect ................................................................................. 97
4.4.1 On-Chip Power Busses .................................................................................... 97
4.4.2 Chip-Package Wirebond and Leadframe ......................................................... 99
4.4.3 Example Models ............................................................................................... 99
4.5 Modeling Chip Substrate ............................................................................ 101
4.5.1 Modeling a 3-D Substrate Layer Cell ............................................................ 102
4.5.2 Modeling Coarse Substrate Meshes of Cells ................................................. 102
4.5.3 Example Models ............................................................................................. 103
4.6 DC Behavior Evaluation Methods ............................................................. 107
4.6.1 Topology-Specific ........................................................................................... 107
4.6.2 Topology-Independent .................................................................................... 107
4.7 AC and Transient Behavior Evaluation Methods ....................................... 10 8
ix
SYNTHESIS OF POWER DISTRIBUTION FOR MIXED-SIGNAL ICS
4.7.1 SPICE-like Approach ..................................................................................... 109
4.7.2 AWE. ............................................................................................................... 109
4.8 Review of Asymptotic Waveform Evaluation (AWE) ............................... 110
4.9 AWE-based Single Input Switching Behavior ........................................... 112
4.10 AWE-based Simultaneous Switching Behavior ......................................... 113
4.11 Concluding Remarks .................................................................................. 115
5 Experimental Results ................................................ 121
5.1 Experimental Plan ...................................................................................... 121
5.2 Example Nonconvex ................................................................................... 124
5.3 Example Analog1 ....................................................................................... 128
5.4 Example Mixed-Signall ............................................................................. 134
5.5 Example Mixed-Signal2 ............................................................................. 135
5.6 Example Mixed-Signal3 ............................................................................. 138
5.7 Example Config1 ........................................................................................ 140
5.8 Example Stanford ....................................................................................... 142
5.8.1 Linear Macromodels ...................................................................................... 145
5.8.2 Power Distribution Synthesis ......................................................................... 147
5.9 Example Mixed-Signal4 ............................................................................. 151
5.9.1 Linear Macromodels ...................................................................................... 153
5.9.2 Power Distribution Synthesis ......................................................................... 155
5.9.3 Effect of Substrate Contacts on Coupled Noise ............................................. 162
5.9.4 Scaling Behavior ............................................................................................ 164
5.10 Example CMU. ........................................................................................... 165
5.10.1Power Distribution Synthesis ......................................................................... 166
5.10.2RAIL. WREN Interface ................................................................................. 168
5.11 SQP and Annealing, Revisited ................................................................... 169
5.12 Concluding Remarks .................................................................................. 173
6 Conclusions ................................................................ 177
6.1 Summary .................................................................................................... 178
6.2 Contributions .............................................................................................. 178
6.3 Future Directions ........................................................................................ 180
x
CONTENTS
A Symbolic Convolution of Special Waveforms .•••.... 183
A.l Specialized Waveforms .............................................................................. 183
A.l.l Trap ................................................................................................................ 183
A.l.2 Sinsq ............................................................................................................... 184
A.2 Fundamental Waveforms ............................................................................ 186
A.2.1 Step ................................................................................................................. 186
A.2.2 ROI7Ip .............................................................................................................. 188
A.2.3 Cosine ............................................................................................................. 190
B Circuit Element Approximation
of Chip Substrate ..................................................... 195
B.l Underlying TreatInent ................................................................................ 195
B.2 General Bulk Field Derivation ................................................................... 196
B.3 Box Integration ........................................................................................... 197
Index ............................................................................. 203
xi
List ofF igures
Chapter 1
1.1 Synthesized power distribution for Mixed-signal3 example ........................ 6
Chapter 2
2.1 Physical design styles ................................................................................. 15
2.2 Slicing structure placement representation ................................................. 17
2.3 Channel sharing effect on congestion ......................................................... 20
2.4 Power supply loading effects on macrocells .............................................. 22
2.5 Power supply mismatch between macrocells ............................................. 23
2.6 Mixed-signal power supply noise generation and coupling ....................... 24
2.7 Mixed-signal physical designs ................................................................... 26
2.8 Power I/O pad cell assignment impact on power bus routing ................... .30
2.9 Power bus topology and sizing interdependence ........................................ 31
Chapter 3
3.1 New optimization-based power distribution strategy ................................ .40
3.2 Slicing structure representation of standard-cell placement.. .................... .42
3.3 Creating the general grid ........................................................................... .44
3.4 Creating a configurable I/O cell. .............................................................. ..47