Switching and Finite Automata Theory, Third Edition

631 Pages·2009·7.42 MB·English

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SwitchingandFiniteAutomataTheory
Understandthestructure,behavior,andlimitationsoflogicmachineswiththis
thoroughlyupdatedthirdedition.
Newtopicsinclude:
(cid:2)
CMOSgates
(cid:2)
logicsynthesis
(cid:2)
logicdesignforemergingnanotechnologies
(cid:2)
digitalsystemtesting
(cid:2)
asynchronouscircuitdesign
The intuitive examples and minimal formalism of the previous edition are
retained,givingstudentsatextthatislogicalandeasytofollow,yetrigorous.
Kohavi and Jha begin with the basics, and then cover combinational logic
design and testing, before moving on to more advanced topics in finite-state
machinedesignandtesting.Thetheoryismadeeasiertounderstandwith200
illustrativeexamples,andstudentscantesttheirunderstandingwithover350
end-of-chapterreviewquestions.
ZviKohaviisExecutiveVicePresidentandDirectorGeneralatTechnion–Israel
Institute of Technology. He is Professor Emeritus of the Computer Science
DepartmentatTechnion,whereheheldthepositionofSirMichaelandLady
SobellChairinComputerEngineeringandElectronics.
NirajK.JhaisaProfessoratPrincetonUniversityandaFellowoftheIEEEand
ACM.HeisarecipientoftheAT&TFoundationAwardandNECPreceptorship
Award for research excellence, the NCR Award for teaching excellence, and
Princeton’sGraduateMentoringAward.
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Switching and Finite
Automata Theory
Third Edition
Zvi Kohavi
Technion–IsraelInstituteofTechnology
Niraj K. Jha
PrincetonUniversity
iii
CAMBRIDGE UNIVERSITY PRESS
Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore,
São Paulo, Delhi, Dubai, Tokyo
Cambridge University Press
The Edinburgh Building, Cambridge CB2 8RU, UK
Published in the United States of America by Cambridge University Press, New York
www.cambridge.org
Information on this title: www.cambridge.org/9780521857482
© Z. Kohavi and N. Jha 2010
This publication is in copyright. Subject to statutory exception and to the
provision of relevant collective licensing agreements, no reproduction of any part
may take place without the written permission of Cambridge University Press.
First published in print format 2009
ISBN-13 978-0-511-65824-2 eBook (NetLibrary)
ISBN-13 978-0-521-85748-2 Hardback
Cambridge University Press has no responsibility for the persistence or accuracy
of urls for external or third-party internet websites referred to in this publication,
and does not guarantee that any content on such websites is, or will remain,
accurate or appropriate.
Contents
Preface pagexi
Part1 Preliminaries
1 Numbersystemsandcodes 3
1.1 Numbersystems 3
1.2 Binarycodes 10
1.3 Errordetectionandcorrection 13
Notesandreferences 19
Problems 20
2 Sets,relations,andlattices 23
2.1 Sets 23
2.2 Relations 25
2.3 Partiallyorderedsets 28
2.4 Lattices 30
Notesandreferences 33
Problems 33
Part2 Combinationallogic
3 Switchingalgebraanditsapplications 37
3.1 Switchingalgebra 37
3.2 Switchingfunctions 44
3.3 Isomorphicsystems 52
3.4 Electronic-gatenetworks 57
∗3.5 Booleanalgebras 58
Notesandreferences 60
Problems 61
v
vi Contents
4 Minimizationofswitchingfunctions 67
4.1 Introduction 67
4.2 Themapmethod 68
4.3 Minimalfunctionsandtheirproperties 78
4.4 Thetabulationprocedureforthedeterminationofprimeimplicants 81
4.5 Theprimeimplicantchart 86
4.6 Map-enteredvariables 93
4.7 Heuristictwo-levelcircuitminimization 95
4.8 Multi-outputtwo-levelcircuitminimization 97
Notesandreferences 100
Problems 101
5 Logicdesign 108
5.1 Designwithbasiclogicgates 108
5.2 Logicdesignwithintegratedcircuits 112
5.3 NANDandNORcircuits 125
5.4 Designofhigh-speedadders 128
5.5 Metal-oxidesemiconductor(MOS)transistorsandgates 132
5.6 AnalysisandsynthesisofMOSnetworks 135
Notesandreferences 143
Problems 144
6 Multi-levellogicsynthesis 151
6.1 Technology-independentsynthesis 151
6.2 Technologymapping 162
Notesandreferences 169
Problems 170
7 Thresholdlogicfornanotechnologies 173
7.1 Introductoryconcepts 173
7.2 Synthesisofthresholdnetworks 181
Notesandreferences 200
Problems 202
8 Testingofcombinationalcircuits 206
8.1 Faultmodels 206
8.2 Structuraltesting 212
8.3 I testing 220
DDQ
8.4 Delayfaulttesting 224
8.5 Synthesisfortestability 232
8.6 Testingfornanotechnologies 250
Notesandreferences 254
Problems 257
vii Contents
Part3 Finite-statemachines
9 Introductiontosynchronoussequentialcircuitsand
iterativenetworks 265
9.1 Sequentialcircuits–introductoryexample 265
9.2 Thefinite-statemodel–basicdefinitions 269
9.3 Memoryelementsandtheirexcitationfunctions 272
9.4 Synthesisofsynchronoussequentialcircuits 280
9.5 Anexampleofacomputingmachine 293
9.6 Iterativenetworks 296
Notesandreferences 300
Problems 300
10 Capabilities,minimization,andtransformation
ofsequentialmachines 307
10.1 Thefinite-statemodel–furtherdefinitions 307
10.2 Capabilitiesandlimitationsoffinite-statemachines 309
10.3 Stateequivalenceandmachineminimization 311
10.4 Simplificationofincompletelyspecifiedmachines 317
Notesandreferences 330
Problems 330
11 Asynchronoussequentialcircuits 338
11.1 Modesofoperation 338
11.2 Hazards 339
11.3 SynthesisofSICfundamental-modecircuits 346
11.4 Synthesisofburst-modecircuits 358
Notesandreferences 363
Problems 365
12 Structureofsequentialmachines 372
12.1 Introductoryexample 372
12.2 Stateassignmentsusingpartitions 375
12.3 Thelatticeofclosedpartitions 380
12.4 Reductionoftheoutputdependency 383
12.5 Inputindependencyandautonomousclocks 386
12.6 Covers,andthegenerationofclosedpartitionsby
statesplitting 388
12.7 Informationflowinsequentialmachines 395
12.8 Decomposition 404
∗12.9 Synthesisofmultiplemachines 413
Notesandreferences 418
Problems 419
viii Contents
13 State-identificationexperimentsandtestingofsequentialcircuits 431
13.1 Experiments 431
13.2 Homingexperiments 435
13.3 Distinguishingexperiments 439
13.4 Machineidentification 440
13.5 Checkingexperiments 442
∗13.6 Designofdiagnosablemachines 448
13.7 Alternativeapproachestothetestingofsequentialcircuits 453
13.8 Designfortestability 458
13.9 Built-inself-test(BIST) 461
Appendix13.1 Boundsonthelengthofsynchronizingsequences 464
Appendix13.2 Aboundonthelengthofdistinguishingsequences 467
Notesandreferences 467
Problems 468
14 Memory,definiteness,andinformationlosslessnessof
finiteautomata 478
14.1 Memoryspanwithrespecttoinput–outputsequences
(finite-memorymachines) 478
14.2 Memoryspanwithrespecttoinputsequences(definitemachines) 483
14.3 Memoryspanwithrespecttooutputsequences 488
14.4 Information-losslessmachines 491
∗14.5 Synchronizableanduniquelydecipherablecodes 504
Appendix14.1 Theleastupperboundforinformationlosslessness
offiniteorder 510
Notesandreferences 512
Problems 513
15 Linearsequentialmachines 523
15.1 Introduction 523
15.2 Inertlinearmachines 525
15.3 Inertlinearmachinesandrationaltransferfunctions 532
15.4 Thegeneralmodel 537
15.5 Reductionoflinearmachines 541
15.6 Identificationoflinearmachines 550
15.7 Applicationoflinearmachinestoerrorcorrection 556
Appendix15.1 Basicpropertiesoffinitefields 559
Appendix15.2 TheEuclideanalgorithm 561
Notesandreferences 562
Problems 563
16 Finite-staterecognizers 570
16.1 Deterministicrecognizers 570
16.2 Transitiongraphs 572